Sato, Yokohama
Akane Sato, Yokohama JP
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20090300349 | VALIDATION SERVER, VALIDATION METHOD, AND PROGRAM - A validation server using HSM, which reduces required process time from receiving a validation request to responding with a validation result, and comprises a first software cryptographic module | 12-03-2009 |
20100122081 | METHOD OF VALIDATION PUBLIC KEY CERTIFICATE AND VALIDATION SERVER - In response to a validation request that includes second information identifying the certificate authority, key information of the certificate authority at issuance of the public key certificate, and information identifying the public key certificate, if the second information identifying the certificate authority included in the validation request corresponds to the first information identifying the certificate authority included in the authority certificate, and the information identifying the public key certificate included in the validation request does not exist in the revocation information, the validation server creates a validation result indicating that the public key certificate corresponding to the information identifying the public key certificate included in the validation request is valid. | 05-13-2010 |
20110004763 | CERTIFICATE VALIDATION METHOD AND CERTIFICATE VALIDATION SERVER AND STORAGE MEDIUM - A certificate validation method for causing a certificate validation server to receive a certificate validation request from a given terminal device, build a certification path of from a first certificate authority (CA) to a second CA, perform validation of the certification path, and send a validation result to the terminal which issued the certificate validation request is disclosed. The validation server detects either a key update of any given CA or a compromise of the given CA, acquires a certificate of relevant CA and first certificate status information and second certificate status information, stores the acquired information in a storage unit or, alternatively, updates the information stored in the storage based on the acquired information, and performs the building of a certification path and validation of the certification path by use of the information of the storage unit. | 01-06-2011 |
20110231662 | CERTIFICATE VALIDATION METHOD AND VALIDATION SERVER - The validation server obtains information related to a first cryptographic method from a certificate which is contained in a certificate validation request from a terminal device. When the information related to the first cryptographic method is not stored in a storage unit of the validation server as valid information, the validation server determines that the information related to the first cryptographic method is invalid. When the information related to the first cryptographic method is stored in the storage unit as valid information and also the information related to a second cryptographic method listed in the certificate in the certification path is not stored in the storage unit during the certification path validation, the validation server determines that the information related to the second cryptographic method is invalid. | 09-22-2011 |
20120159158 | VALIDATION SERVER, VALIDATION METHOD, AND PROGRAM - A validation server using HSM, which reduces required process time from receiving a validation request to responding with a validation result, and comprises a first software cryptographic module | 06-21-2012 |
20130061043 | METHOD OF VALIDATION PUBLIC KEY CERTIFICATE AND VALIDATION SERVER - In response to a validation request that includes second information identifying the certificate authority, key information of the certificate authority at issuance of the public key certificate, and information identifying the public key certificate, if the second information identifying the certificate authority included in the validation request corresponds to the first information identifying the certificate authority included in the authority certificate, and the information identifying the public key certificate included in the validation request does not exist in the revocation information, the validation server creates a validation result indicating that the public key certificate corresponding to the information identifying the public key certificate included in the validation request is valid. | 03-07-2013 |
Akihisa Sato, Yokohama JP
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20090006780 | Storage system and path management method - A storage system and a path management method, which can facilitate node replacement are proposed. In the storage system, the host sets plural paths between the host and the volume and holds path information composed of management information on each of the paths; and the management apparatus includes an integrated path management unit that collects the path information on each of the paths defined between the host and the volume from the corresponding host to manage all the collected information as integrated path information; retrieves an alternate path going through a node other than a specified node and but that has the same function as the specified node, for the path going through the specified node, based on the integrated path information; and displays results of the retrieval. | 01-01-2009 |
20120005327 | STORAGE SYSTEM AND PATH MANAGEMENT METHOD FOR MULTI-HOST ENVIRONMENT - A storage system and a path management method, which can facilitate node replacement, are proposed. In the storage system, the host sets plural paths between the host and the volume and holds path information composed of management information on each of the paths. The management apparatus includes an integrated path management unit that collects the path information on each of the paths defined between the host and the volume from the corresponding host to manage all the collected information as integrated path information; retrieves an alternate path going through a node other than a specified node but that has the same function as the specified node, for the path going through the specified node, based on the integrated path information; and displays results of the retrieval. | 01-05-2012 |
Atsuhiko Sato, Yokohama JP
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20090117898 | Base Station and Mobile Station - Problems can be solved by a base station to which a location of a mobile station is registered and which performs a radio communication with the MS, and when receiving distribution information, divides the distribution information into N pieces, and incorporates the divided distribution information in N pieces of reception channels to successively transmit them to the MS. It can be achieved by a MS which is in a waiting state of a BS and which performs a radio communication with the BS, and when receiving distribution information which is incorporated in reception channels and divided, stores the distribution information, and when determining completion of the distribution of the distribution information, constructs the N pieces of divided information and displays it. | 05-07-2009 |
Atsuhito Sato, Yokohama JP
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20080279124 | OFDM WIRELESS COMMUNICATION METHOD AND WIRELESS COMMUNICATION APPARATUS - In a wireless communication system wherein at least two communication units employ the TDD wireless communication method based on OFDMA, an OFDM wireless communication method and a wireless communication apparatus are disclosed. The first communication unit transmits a pilot signal over the whole subband zone configured of divisions of a predetermined system band. The second communication unit having a plurality of antennas estimates a propagation path of the subchannels constituting continuous frequency blocks making up a subband from the pilot signal received. The second communication unit determines the array weight used at the time of signal transmission to the first communication unit using the estimation result. | 11-13-2008 |
Aya Sato, Yokohama JP
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20140050078 | COMMUNICATION INTERRUPTION TIME REDUCTION METHOD IN A PACKET COMMUNICATION NETWORK - In a redundant packet communication path including an active path and a backup path, user data that flows into the active path during a time when switching from the active path to the backup path is completed is transferred to a device at a protection zone receiving end to reduce a communication interruption time (traffic suspension time) in a user's point of view. | 02-20-2014 |
Ikuro Sato, Yokohama JP
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20150134578 | DISCRIMINATOR, DISCRIMINATION PROGRAM, AND DISCRIMINATION METHOD - A discriminator based on supervised learning includes a data expanding unit and a discriminating unit. The data expanding unit performs data expansion on unknown data which is an object to be discriminated in such a manner that a plurality of pieces of pseudo known data are generated. The discriminating unit applies the plurality of pieces of unknown pseudo data that has been expanded by the data expansion unit to a discriminative model so as to discriminate the plurality of pieces of pseudo unknown data, and integrates discriminative results of the plurality of pieces of pseudo unknown data to perform class classification such that the unknown data is classified into classes. | 05-14-2015 |
20150134583 | LEARNING APPARATUS, LEARNING PROGRAM, AND LEARNING METHOD - A learning apparatus performs a learning process for a feed-forward multilayer neural network with supervised learning. The network includes an input layer, an output layer, and at least one hidden layer having at least one probing neuron that does not transfer an output to an uppermost layer side of the network. The learning apparatus includes a learning unit and a layer quantity adjusting unit. The learning unit performs a learning process by calculation of a cost derived by a cost function defined in the multilayer neural network using a training data set for supervised learning. The layer quantity adjusting unit removes at least one uppermost layer from the network based on the cost derived by the output from the probing neuron, and sets, as the output layer, the probing neuron in the uppermost layer of the remaining layers. | 05-14-2015 |
Kazushi Sato, Yokohama JP
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20130188693 | CHROMA QUANTIZATION PARAMETER EXTENSION - The quantization parameters (QP) for Chroma are extended up to and more preferably to the same range as Luma QP (e.g., 0 to 51). Previous, values of Chroma QP only extended up to 39. Techniques are provided for determining extended Chroma QP values (e.g., for Cr and Cb) based on the Luma QP and picture level chroma offsets. In one preferred embodiment, slice level offsets are added making the method particularly well-suited for slice level parallel processing. The extension of Chroma QP enhances functionality, flexibility and friendliness of the High Efficiency Video Coding (HEVC) standard for various applications. | 07-25-2013 |
20140003487 | VIDEO CODING SYSTEM WITH TEMPORAL LAYERS AND METHOD OF OPERATION THEREOF | 01-02-2014 |
20140003535 | VIDEO CODING SYSTEM WITH LOW DELAY AND METHOD OF OPERATION THEREOF | 01-02-2014 |
Keiichi Sato, Yokohama JP
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20110252336 | INFORMATION MANAGEMENT SUPPORT METHOD, MANAGEMENT INFORMATION VISUALIZATION DEVICE, INFORMATION MANAGEMENT SYSTEM, AND MANAGEMENT INFORMATION VISUALIZATION METHOD - A management information visualization device (management provider server | 10-13-2011 |
20140172830 | SECURE SEARCH PROCESSING SYSTEM AND SECURE SEARCH PROCESSING METHOD - A secure search processing system includes an information processing apparatus that calculates an exclusive OR of second information obtained by applying a keyword for search to a one-way function and a second random number obtained with a random number generator, calculates an exclusive OR of a search value that is the calculation result and registration values in a database, and calculates an exclusive OR of a value obtained by applying to the homomorphic function a calculation result of an exclusive OR of a value of a search value and registration values and a value obtained by applying a second random number to a homomorphic function, searches for an output value of the one-way function with which registration values in the database are associated using as a key a value obtained by applying a calculation result to the one-way function, and outputs a search result to an output interface. | 06-19-2014 |
Keishi Sato, Yokohama JP
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20110244262 | Metal Bonding Member and Fabrication Method of the Same - Provided are a metal bonding member having both a high adhesion strength and an excellent heat cycle reliability and a fabrication method of the same. A metal bonding member has a solder layer formed on at least a part of the surface of a metal substrate. The metal bonding member has an adhesion layer formed of metal particles having an excellent wettability with the solder layer in the interface between the solder layer and the metal substrate. The adhesion layer is partially buried in the metal substrate to form an anchor layer. | 10-06-2011 |
Kenichiro Sato, Yokohama JP
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20140187659 | COMPOSITION FOR ELECTRONIC DEVICE - The present invention provides a composition of which viscosity does not cause the problem of use at high temperature in the mounting process of electronic device. The present invention relates to a composition for electronic device comprising (a) a (meth)acrylic compound and (c) a particle having a functional group having metal scavenging functionality. | 07-03-2014 |
20140187714 | SEALANT COMPOSITION FOR ELECTRONIC DEVICE - The present invention provides a sealant composition for electronic device, in which the curing does not proceed when heated, which does not cause the problem of use in the mounting process of electronic device. The present invention relates to a sealant composition for electronic device comprising (a) a compound having two or more (meth)acryloyl groups and (c) a nitroxide compound and/or a thiocarbonylthio compound. | 07-03-2014 |
20140187729 | UNDERFILL SEALANT COMPOSITION - The present invention provides a composition which does not cause the problem of use at high temperature in the mounting process of electronic device. The present invention relates to an underfill sealant composition comprising (a) a (meth)acrylic compound and (c) an isocyanuric acid having an allyl group. | 07-03-2014 |
Kyoji Sato, Yokohama JP
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20110185152 | RECONFIGURABLE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction. | 07-28-2011 |
20110246747 | RECONFIGURABLE CIRCUIT USING VALID SIGNALS AND METHOD OF OPERATING RECONFIGURABLE CIRCUIT - A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed. | 10-06-2011 |
Michio Sato, Yokohama JP
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20150152540 | COMPONENT FOR PLASMA PROCESSING APPARATUS AND METHOD FOR MANUFACTURING COMPONENT FOR PLASMA PROCESSING APPARATUS - The present invention provides a component for a plasma processing apparatus, the component comprising: a base material; an underlayer covering a surface of the base material; and an yttrium oxide film covering a surface of the underlayer, wherein the underlayer comprises a metal oxide film having a thermal conductivity of 35 W/m·K or less, the yttrium oxide film contains at least either particulate portions made of yttrium oxide or non-particulate portions made of yttrium oxide, the particulate portions being portions where a grain boundary demarcating an outer portion of the grain boundary is observed under a microscope, and the non-particulate portions being portions where the grain boundary is not observed under a microscope, the yttrium oxide film has a film thickness of 10 μm or more and a film density of 96% or more, and when a surface of the yttrium oxide film is observed under a microscope, an area coverage ratio of the particulate portions is 0 to 20% in an observation range of 20 μm×20 μm and an area coverage ratio of the non-particulate portions is 80 to 100% in the observation range. | 06-04-2015 |
Nagahisa Sato, Yokohama JP
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20140158622 | RECOVERY METHOD AND DRAW SOLUTION FOR FORWARD OSMOSIS - The present disclosure relates to a water recovery method and an FO draw solution that reduce the energy consumption required for water recovery, increase the osmotic pressure of a draw solution, recover the water from a DS mixed solution relatively easily, and reduce a solute that remains in the water, and simultaneously reduce fouling of the FO membrane. The water recovery method may include inflowing water into a draw solution by partitioning a feed solution including water and a draw solution, including a basic temperature-sensitive polymer and an acidic gas dissolved therein and having higher osmotic pressure than the feed solution, with a forward osmosis membrane. | 06-12-2014 |
Naoyuki Sato, Yokohama JP
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20090280577 | Manufacturing method of a semiconductor device - There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode. | 11-12-2009 |
Nobuaki Sato, Yokohama JP
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20090103406 | Optical disc drive - There is provided an optical disc drive comprises an optical pick-up including a laser diode (LD) and a laser diode driver (LDD) for driving the laser diode, a digital signal processor (DSP) including a write strategy circuit and low voltage differential signaling (LVDS) drivers for transmitting a produced write strategy signal, a circuit board having the DSP mounted thereon and including a line for transmitting the write strategy signal, a transmission line connecting the circuit board and the LDD and transmitting a write strategy signal, and differential resistors connected between differential lines of outputs of the LVDS drivers. Especially, a resistor having a resistance value in a range of 80 to 500Ω is inserted between the differential lines of outputs of the LVDS driver inside the DSP. | 04-23-2009 |
20120039001 | DISK LIBRARY APPARATUS - A disk library apparatus includes a magazine for housing a plurality of storage disks, a plurality of pallets each having a disk placing surface for placing a storage disk and which are arranged in the magazine so that pallets having different engaging claw shapes are adjacent to each other, and a picker for taking out a pallet selected from the plurality of pallets from the magazine. The picker includes at least one arm for taking out the selected pallet from the magazine in the taking-out of the selected pallet. Each of the at least one arm is, in the taking-out of the selected pallet, engaged with an engaging claw of the selected pallet and in a position shifted from an engaging position with an engaging claw of each pallet adjacent to the selected pallet when seen in a pallet arranging direction. | 02-16-2012 |
Ryohei Sato, Yokohama JP
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20140091693 | ELECTRONIC DEVICE AND ELASTIC SLIDE LOCK MEMBER - An electronic device includes: a housing provided with an opening that accommodates a component; a cover member that covers the opening; a projecting part that projects from an inside face of the housing; a slide knob slidably provided to a surface of the housing; and an elastic slide lock member that fixes the cover member to the housing, wherein the elastic slide lock member includes: a movement part that is coupled to the slide knob, moves together with the slide knob, and is provided with a fixing projection; a fixing part that is rotatably supported by the projecting part of the housing; and a coupling part that couples the movement part and the fixing part and is elastically deformable. | 04-03-2014 |
Ryuichiro Sato, Yokohama JP
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20120251068 | OPTICAL FIBER HOLDER AND METHOD FOR HOLDING COATED OPTICAL FIBER - An optical fiber holder includes a holder main body and cord receiving groove. The holder main body has a fiber receiving groove and a first cord receiving groove. The fiber receiving groove receives and positions a coated optical fiber of an optical fiber cord with a cord jacket removed at the tip of the optical fiber cord. The cord receiving groove receives the cord jacket. A cord holding cover and a fiber pressing cover | 10-04-2012 |
20130236145 | OPTICAL FIBER FUSION SPLICER - An optical fiber fusion splicer includes positioning members and clamping members. Each clamping member clamps the bare fiber. A first guiding portion protrudes from the top surface of each positioning member and guides a distal end portion of the bare fiber toward the groove. A concave face of the first guiding portion has a V-shaped cross section. Each clamping member includes a second guiding portion, which guides a base portion of the bare fiber toward the groove of the corresponding positioning member, and a pressing member, which presses the bare fiber against the top surface of the fiber positioning member. A concave face of the second guiding portion has an inverted-V-shaped cross section. The fusion splicer can clamp bare fibers while the bare fibers are received by the groove. | 09-12-2013 |
Shuhei Sato, Yokohama JP
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20100235686 | EXECUTION HISTORY TRACING METHOD - An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target. | 09-16-2010 |
20100251022 | INTEGRATED CIRCUIT, DEBUGGING CIRCUIT, AND DEBUGGING COMMAND CONTROL METHOD - An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation. | 09-30-2010 |
20140075249 | Execution History Tracing Method - An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target. | 03-13-2014 |
Shuheui Sato, Yokohama JP
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20140201403 | DEBUG CONTROL CIRCUIT - An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation. | 07-17-2014 |
Shuri Sato, Yokohama JP
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20150179943 | ORGANIC ELECTROLUMINESCENCE DEVICE - An organic electroluminescence device includes an anode, a hole transport layer on the anode, the hole transport layer including a plurality of layers having different compounds as main components, an emission layer on the hole transport layer, and a cathode on the emission layer. A hole mobility of a first layer of the hole transport layer having the greatest thickness among the plurality of layers of the hole transport layer is greater than a hole mobility of at least one layer of the hole transport layer between the first layer of the hole transport layer and the emission layer. | 06-25-2015 |
Toshiya Sato, Yokohama JP
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20110272742 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFCTURING SAME - A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer. | 11-10-2011 |
20120235210 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD AND TRANSISTOR CIRCUIT - A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor. | 09-20-2012 |
20130228827 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD AND TRANSISTOR CIRCUIT - A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor. | 09-05-2013 |
20140021513 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer. | 01-23-2014 |
Yasuharu Sato, Yokohama JP
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20110205808 | SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program operation, sets one of the source lines coupled to a row of the memory cells including a program memory cell to a high level voltage, and sets at least one of the remaining source lines coupled to a row of a non-program memory cells to be higher than a low level voltage of the selection gate lines and to be lower than the high level voltage of an unselection bit line. Thereby, a leak current lowering a voltage of the source lines at the time of program operation can be blocked off, and a program operation time may be shortened. | 08-25-2011 |
Yoshifumi Sato, Yokohama JP
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20080231427 | TRACEABILITY SYSTEM - An individual article management system for managing an individual article distributed through a plurality of sites with a form thereof changed at least one of the plurality of sites. Each of the information processing apparatuses transmits read identification information and formed index data to a data center apparatus through a network, and the data center apparatus, receives the transmitted identification information and the transmitted index data, and stores each of the received index data into a storing apparatus so as to be associated with each other on the basis of the identification information for identifying the individual article. | 09-25-2008 |
20090160624 | TRACEABILITY SYSTEM - An individual article management arrangements for managing an individual article distributed through a plurality of sites with a form thereof changed at least one of said plurality of sites, including: information processing apparatuses installed at said plurality of sites; and a data center apparatus connected to each of said information processing apparatuses through a network. The data center apparatus and the information processing apparatuses are configured to effect predetermined operations. | 06-25-2009 |
Yukinari Sato, Yokohama JP
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20130291444 | CMP SLURRY REGENERATION APPARATUS AND METHOD - The CMP slurry regeneration apparatus | 11-07-2013 |