Sathe, US
Abhijit Sathe, Charlotte, NC US
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20120268227 | EMBEDDED COOLING OF WOUND ELECTRICAL COMPONENTS - A pumped liquid multiphase transformer cooling system utilizes a cold plate evaporator positioned between, insulated from, and in thermal contact with, the core and winding of the transformer. The system includes a condenser and a pump to move the multiphase refrigerant through the cold plate and the condenser and back to the pump. | 10-25-2012 |
Abhijit Ashok Sathe, Fort Wayne, IN US
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20120044032 | PUMPED LOOP REFRIGERANT SYSTEM FOR WINDINGS OF TRANSFORMER - A pumped loop cooling system is provided to cool a hollow winding of a transformer utilizing a two phase vaporizable dielectric refrigerant. A liquid refrigerant pump circulates the refrigerant into a transformer and through a copper tube winding of the transformer where the refrigerant at least partially vaporizes in removing heat from the transformer. The refrigerant is then circulated to a condenser and then back to the pump. | 02-23-2012 |
Abhijit Ashok Sathe, Charlotte, NC US
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20120186290 | PUMPED LOOP DRIVEN VAPOR COMPRESSION COOLING SYSTEM - A cooling system is provided that combines a two-phase refrigerant pumped loop cooling circuit and a vapor compression loop circuit in a complete electronics cooling package for use in high ambient temperature applications. Specific applications may include, but are not limited to, power electronics converter and inverter drives, and hybrid electric vehicles. In hybrid electric vehicle applications, the primary pumped two-phase refrigerant cooling system is used for providing high-temperature cooling to the inverter drive. The secondary vapor compression system is used to provide low-temperature cooling to the battery module (i.e. such as Li-ion cells) or passenger compartment cooling, thereby eliminating the need for a special cooling solution for the battery module which requires lower temperature cooling. | 07-26-2012 |
Ajit V. Sathe, Chandler, AZ US
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20090152738 | INTEGRATED CIRCUIT PACKAGE HAVING BOTTOM-SIDE STIFFENER - Embodiments of a bottom-side stiffening element are disclosed. The stiffening element may be disposed between an integrated circuit package and an underlying circuit board. In some embodiments, the stiffening element is attached to the underlying circuit board. Other embodiments are described and claimed. | 06-18-2009 |
20130005162 | MULTIPLE SOCKET CONCEPT - Electronic assemblies and their manufacture are described. One assembly includes a land grid array package including a plurality of land contacts. The assembly also includes a first socket adapted to engage a first group of the plurality of land contacts, and a second socket adapted to engage a second group of the plurality of land contacts. The first socket and the second socket are each coupled to a board. The first socket and the second socket are separate structures on the board. Other embodiments are described and claimed. | 01-03-2013 |
Aruna Sathe, Sierra Madre, CA US
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20140379272 | LIFE ANALYSIS SYSTEM AND PROCESS FOR PREDICTING AND FORECASTING LIFE EVENTS - A process for predicting and forecasting life events and a system that performs a life analysis of a person and predicts life events, milestones, and other life paths are disclosed. Predictability and intelligent forecasting of life statuses, milestones, and achievements are provided through a unique combination of algorithms, heuristic rules, data analytics and digitization. | 12-25-2014 |
Madhura Sathe, Charlotte, NC US
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20090046950 | SYSTEM AND METHOD OF DETERMINING IMAGE SKEW USING CONNECTED COMPONENTS - A system and method for determining skew of a document image. An image processing system is provided, comprising: an image segmentation system that identifies and segments a line of printed characters; and a skew processing system that determines the skew by calculating slope values for pairs of characters in the line. | 02-19-2009 |
20090116725 | GRAY SCALE IMAGE CLEANING SYSTEM AND METHOD - A gray scale image cleaning algorithm for improved check code line OCR. An image processing system for processing a gray scale image is provided that includes: a system for generating a first thresholded black white image from the gray scale image; a system for generating a second thresholded black white image from the gray scale image, wherein the second thresholded black white image is generated with a higher threshold value than the first thresholded black white image; and a system for logically combining the first and second thresholded black white images to generate a composite image. | 05-07-2009 |
20100195895 | SOLUTION FOR DETECTING A STREAK IN A COMPRESSED GRAY SCALE IMAGE - A solution for detecting a streak in a JPEG image is disclosed that includes an extraction system for extracting a DC value from each cell block in the compressed image; an identification system for identifying a peak DC value in each rank of cell blocks within the compressed image; and an analysis system for analyzing the peak DC values to determine if a streak exists in the compressed image. | 08-05-2010 |
Madhura A. Sathe, Charlotte, NC US
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20080199067 | SYSTEM FOR DETERMINING IMAGE RESOLUTION USING MICR CHARACTERS - A system for determining the image resolution of a check image using MICR characters. The disclosed system includes an extracting system for extracting a magnetic ink code recognition (MICR) code line from the document image, wherein the extracting system provides coordinate values for each of a plurality of MICR characters in the MICR code line; a calculating system for calculating a set of resolution values based on the coordinate values of the MICR characters; and a statistical analysis system that calculates a representative resolution value from the set of resolution values. | 08-21-2008 |
Nikhil S. Sathe, Monte Sereno, CA US
Patent application number | Description | Published |
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20120191553 | POINT OF SALE PAYMENT SYSTEM - A method for point of sale payments includes receiving, from a seller device over a network, payment information. The payment information is associated with payment code information in a database. The payment code information is then sent to the seller device over the network for posting at a service location. The payment code information is then captured by a payer device at the service location and transmitted over the network. The payment information is then retrieved from the database using the associated payment code information. The payment information is then sent to the payer device over the network. A payment confirmation is received from the payer device over the network and, in response, a payment from a payer account to a seller account is initiated and the payment information and an indication of the payment confirmation is sent to the seller device over the network. | 07-26-2012 |
20120246018 | POINT OF SALE PAYMENT SYSTEM - A method for point of sale payments includes receiving, from a seller device over a network, payment information. The payment information is associated with payment code information in a database. The payment code information is then sent to the seller device over the network for posting at a service location. The payment code information is then captured by a payer device at the service location and transmitted over the network. The payment information is then retrieved from the database using the associated payment code information. The payment information is then sent to the payer device over the network. A payment confirmation is received from the payer device over the network and, in response, a payment from a payer account to a seller account is initiated and the payment information and an indication of the payment confirmation is sent to the seller device over the network. | 09-27-2012 |
20140006278 | SAVE TO OPEN WALLET | 01-02-2014 |
Rahul Sathe, Cambridge, MA US
Patent application number | Description | Published |
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20130103074 | METHOD AND APPARATUS FOR RESTRICTING FLOW THROUGH AN OPENING IN THE SIDE WALL OF A BODY LUMEN, AND/OR FOR REINFORCING A WEAKNESS IN THE SIDE WALL OF A BODY LUMEN, WHILE STILL MAINTAINING SUBSTANTIALLY NORMAL FLOW THROUGH THE BODY LUMEN - A device comprising a single closed loop of elastic filament configurable between (i) a first configuration for movement along a blood vessel; and (ii) a second configuration for lodging within a blood vessel, the second configuration providing a single flow-restricting face sized and configured to cover the mouth of the aneurysm and obstruct blood flow to the aneurysm while permitting substantially normal blood flow through the blood vessel, with the degree of obstruction at the mouth of the aneurysm being such that the aneurysm thromboses when the face is positioned over the aneurysm, the flow-restricting face comprising a plurality of lengths of the closed loop of filament disposed in close proximity to one another in a switchback configuration, and at least one leg for holding the flow-restricting face adjacent the mouth of the aneurysm, the leg configured so as to maintain substantially normal blood flow through the blood vessel. | 04-25-2013 |
Rahul Sathe, Somerville, MA US
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20150150436 | METHOD AND APPARATUS FOR MANIPULATING THE SIDE WALL OF A BODY LUMEN OR BODY CAVITY SO AS TO PROVIDE INCREASED VISUALIZATION OF THE SAME AND/OR INCREASED ACCESS TO THE SAME, AND/OR FOR STABILIZING INSTRUMENTS RELATIVE TO THE SAME - Apparatus comprising: a sleeve adapted to be slid over the exterior of an endoscope; a proximal balloon secured to the sleeve; an inflation/deflation tube carried by the sleeve and in fluid communication with the interior of the proximal balloon; a push tube slidably mounted to the sleeve; and a distal balloon secured to the distal end of the push tube, the interior of the distal balloon being in fluid communication with the push tube, wherein the distal balloon is capable of assuming a deflated condition and an inflated condition, and further wherein when the distal balloon is in its deflated condition, an axial opening extends therethrough, the axial opening being sized to receive the endoscope therein, and when the distal balloon is in its inflated condition, the axial opening is closed down. | 06-04-2015 |
Rahul Dilip Sathe, San Clemente, CA US
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20080269879 | Implantable Prosthetic Vascular Valve - The present disclosure generally relates to implantable, prosthetic vascular valves, methods of making the valves, and methods of using the valves, in particular, in the human venous system. | 10-30-2008 |
Rahul P. Sathe, Hillsboro, OR US
Patent application number | Description | Published |
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20080294709 | Processing geometric data using spectral analysis - In one embodiment, the present invention includes a method for receiving vertex data corresponding to a surface of an image, performing a discrete Fourier transform (DFT) on the vertex data to obtain a frequency response, zero padding the frequency response to obtain zero padded frequency response data, and performing an inverse DFT (IDFT) on the zero padded frequency response data to obtain modified vertex data including the vertex data and additional vertex data corresponding to the surface. Other embodiments are described and claimed. | 11-27-2008 |
20090033659 | Real-time luminosity dependent subdivision - In one embodiment, the present invention includes a method for receiving geometry data corresponding to a plurality of polygons of a scene, calculating a luminosity metric for each polygon, and subdividing a polygon into multiple polygons if the luminosity metric is greater than a threshold level. Other embodiments are described and claimed. | 02-05-2009 |
20100158388 | Hardware accelerated silhouette detection - Disclosed herein are approaches for detecting and/or generating silhouettes, in graphics processing applications, of objects (e.g., convex objects such as polyhedrons). | 06-24-2010 |
20100164954 | Tessellator Whose Tessellation Time Grows Linearly with the Amount of Tessellation - In accordance with some embodiments, a tessellator may experience only a linear increase in tessellation time with increasing edge levels of detail. Conventionally, tessellators experience a non-linear or quadratic increase in tessellation time with increasing levels of detail. In some embodiments, the intervals and the triangulation of the inner tessellation may be pre-computed. Then at run time, the pre-computed values may be looked up for the applicable edge level of detail. | 07-01-2010 |
20100164955 | Image forming techniques - In some embodiments, the intervals and the triangulation of an inner tessellation of a patch may be pre-computed. Even factor tessellations are arranged in a co-centric manner so that lower number factors are inside tessellations with higher number factors. Similarly, odd factor tessellations are arranged in a co-centric manner so that lower number factors are inside tessellations with higher number factors. Domain points of even factor tessellations are stored in a first table whereas domain points of odd factor tessellations are stored in a second table. At run time, the pre-computed values may be looked up for the applicable edge level of detail. | 07-01-2010 |
20110102437 | Performing Parallel Shading Operations - A graphics processing pipeline may include at least two or more pipes, such that a lower frequency operation may be executed on one pipe while a higher frequency operation in the same instruction stream is executed at the same time on another pipe. In some cases, the lower frequency operation result may be held for later use in connection with the higher frequency operation on a different pipe. Especially where unused slots can be used for the lower frequency operation, efficiency may be improved. | 05-05-2011 |
Rahul P. Sathe, Folsom, CA US
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20110216068 | Edge processing techniques - In some embodiments, an edge cache data table for edges shared by two or more geometrically contiguous patches is generated. An identification value is assigned for each patch. When a first patch has a common edge with a second patch, a unique identification value is generated for an entry in the table based on identification values of the two patches with a common edge. Attributes of a common edge are stored in the entry in the table associated with the unique identification value. When the common edge is to be evaluated for the second patch, the edge can be read from the table in reverse order. | 09-08-2011 |
Rahul P. Sathe, Emeryville, CA US
Patent application number | Description | Published |
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20130257891 | Post Tesellation Edge Cache - In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed. | 10-03-2013 |
20140198120 | Reducing the Domain Shader/Tessellatorinvocations - In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed. | 07-17-2014 |
20150091913 | TECHNIQUES AND ARCHITECTURE FOR IMPROVED VERTEX PROCESSING - An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value. | 04-02-2015 |
20160078672 | Deferred Coarse Pixel Shading - A shading rate may be set by analyzing samples within a pixel. Then based on that analysis, a system determines whether to use coarse pixel, pixel or sample shading for a region of pixels. Based on the determined type of shading, the shading rate may be set. | 03-17-2016 |
Rhishikesh Ashok Sathe, Kirkland, WA US
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20130342806 | PIEZO BEAM DEVICE - This document describes techniques and apparatuses for implementing a piezo beam device that is configured to excite vibration in a pinna of an ear of a listener to generate audio for the ear. In some embodiments, the piezo beam device is mounted to one or both temple arms of a pair of eyeglasses to enable the piezo beam device to generate audio for one or both ears of a wearer of the pair of eyeglasses. | 12-26-2013 |
Saleel Sathe, Redmond, WA US
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20080235204 | Using user feedback to improve search results - The invention discloses a system and method for managing feedback data that will be used for ranking search results. The invention can aggregate a plurality of user feedback data from more than one user into a search index. The user feedback data can be associated with one or more documents within the index such that the one or more documents can be ranked based on the type of feedback data that is aggregated. Once the documents have been ranked, the ranked documents can be provided to a requester. | 09-25-2008 |
Saleel Sathe, Sammamish, WA US
Patent application number | Description | Published |
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20080320010 | SENSITIVE WEBPAGE CONTENT DETECTION - Computer-readable media, systems, and methods for sensitive webpage content detection are described. In embodiments, a multi-class classifier is developed and one or more webpages with webpage content are received. In various embodiments, the one or more webpages are analyzed with the multi-class classifier and, in various embodiments, a sensitivity level is predicted that is associated with the webpage content of the one or more webpages. In various other embodiments, the multi-class classifier includes one or more sensitivity categories. | 12-25-2008 |
20140007155 | BRAND DETECTION IN AUDIOVISUAL MEDIA | 01-02-2014 |
20140150004 | CONDUCTING ADVERTISING EFFECTIVENESS SURVEYS - Embodiments for generating advertising effectiveness surveys are presented. One example method, performed in a computing device comprising a data-holding subsystem and logic subsystem, comprises receiving a request, the request associated with an identified user, from a video presentation device for a video content item, and providing the video content item to the video presentation device. Information relating to an image analysis is received in order to identify one or more image elements in the video content item, and information regarding user playback actions during playback of the video content item is received and stored. A user survey based upon the information related to the image analysis and the user playback actions is automatically retrieved, the user survey is sent to a device associated with the identified user, and a response to the user survey is received. | 05-29-2014 |
20140150006 | Brand Detection in Audiovisual Media - This document describes techniques and apparatuses enabling brand detection in audiovisual media. The techniques detect a brand exposed within audiovisual media, such as a name or logo for a product or service, and based on this brand, present a brand advertisement or enable selection of an interactive experience that is associated with the brand. By so doing, marketers enable viewers to quickly and easily learn more about the product or service. | 05-29-2014 |
Satish Sathe, San Ramon, CA US
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20110022871 | System-On-Chip Queue Status Power Management - A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold. | 01-27-2011 |
20140201481 | DOMAIN PROTECTION AND VIRTUALIZATION FOR SATA - Various aspects provide for a hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual VMs. The lightweight SATA virtualization handler can also perform the scheduling of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the system processor and has commands from one or more VMs. | 07-17-2014 |
Satish Prabhakar Sathe, San Ramon, CA US
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20110058474 | CONGESTION-ADAPTIVE COMPRESSION - A network device is adaptively configured to compress an output data stream, responsive to congestion in the network. The network device receives indications of network congestion from another network device. Upon receipt of a congestion indication, the network device can adapt the compression technique to attempt to achieve more or less compression, depending on whether the congestion indication indicates more or less congestion. By adapting the compression to the level of network congestion, end-to-end latency of the network can potentially be decreased. | 03-10-2011 |
Shridhar K. Sathe, Tallahassee, FL US
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20090092959 | Nucleic acid and allergenic polypeptides encoded thereby in cashew nuts - The invention describes an isolated nucleic acid sequence comprising the nucleotide sequence of SEQ ID NO:1 or a degenerate variant of SEQ ID NO: 1. The nucleic acid sequence encodes an Ig-E binding immunogenic polypeptide the amino acid sequence of which comprises at least one sequence selected from SEQ ID NOS:4-25. The invention additionally provides an in vitro diagnostic test for detecting anti-cashew IgE in a patient. The test comprises reacting the patient's serum with a purified polypeptide the amino acid sequence of which comprises at least one sequence selected from SEQ ID NOS:3-25; separating the polypeptide from unreacted patient serum; reacting the polypeptide with a labeled human IgE-reactive agent after separating from unreacted patient serum; separating the polypeptide from unreacted labeled human IgE-reactive agent; and detecting labeled human IgE-reactive agent bound to the polypeptide after separating from unreacted agent to thereby indicate presence in the patient's serum of anti-cashew IgE. | 04-09-2009 |
Shridhar K. Sathe, Tallahahassee, FL US
Sonal Sathe, North Bergen, NJ US
Patent application number | Description | Published |
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20090068162 | Stationary Phase Antibody Arrays for Trace Protein Analysis - The present invention relates to the identification of trace proteins and biomarkers, e.g., TH-1/TH-2, cytokines, MMPs and angiogenic modulators in tear fluids. The present invention provides an antibody-based stationary phase array assay for simultaneously identifying, detecting and characterizing the distribution of a wide range of bioactive trace proteins in a tear fluid sample. A method for simultaneously identifying trace proteins in a biological fluid sample using a highly sensitive antibody-array assay is provided. The present invention also provides methods and kits for treating, preventing, and diagnosing ocular diseases, disorders or pathological conditions. | 03-12-2009 |
Tejas Pravin Sathe, San Diego, CA US
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20150312959 | TRANSMITTING DATA OUTSIDE OF A DISCONTINUOUS TRANSMIT (DTX) CYCLE IN WIRELESS COMMUNICATIONS - Aspects described herein relate to transmitting hybrid automatic repeat/request (HARQ) data in continuous packet connectivity (CPC) mode. Data is transmitted to a network according to a discontinuous transmit (DTX) cycle in a CPC mode. The CPC mode can be exited, however, based at least in part on detecting available HARQ data for transmission. In this regard, a next transmission opportunity configured for transmitting the available HARQ data is determined, where the next transmission opportunity is not within a transmission time instance defined by the DTX cycle, and the available HARQ data is transmitted during the next transmission opportunity outside of the CPC mode. | 10-29-2015 |
Tushar R. Sathe, Cedar Knolls, NJ US
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20160089530 | Medical Device Cap for Drug Transfer Assembly - A medical device cap that protectively surrounds a medical device component for disinfection purposes and includes an identification element that can record and transmit pertinent information of the medical device cap and the medical device component is disclosed. The medical device cap enables documentation of instances when the cap is used and promotes stronger compliance with the use of medical device caps for applications involving disinfection of a medical device component such as an IV access port or a luer tip. Use of the medical device cap results in better compliance and monitoring of the use of such caps and leads to reduced incidence of CRBSI infections related to medical device component contamination. In one embodiment, the medical device cap enables automated real-time electronic documentation of when the cap is applied, while also documenting duration of application and tracking of device for inventory management. | 03-31-2016 |
Vandana Sathe, Saratoga, CA US
Patent application number | Description | Published |
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20140067407 | PERSONAL USER DASHBOARD - Systems, methods, and other embodiments associated with a personal user dashboard are described. In one embodiment, a method includes extracting, from one or more databases, case processing information about adverse events processed by a group of users. The one or more databases store data about a plurality of adverse events processed by the group of users. The example method may also include calculating metrics using the case processing information. The metrics are performance indicators about processing of the plurality of adverse events by the group of users. The method includes displaying, on a graphical user interface (GUI), user metrics for a user of the group of users. The user metrics are displayed by filtering confidential data from the metrics. The access privileges of the user are limited to a user level access to prevent access to group level data. | 03-06-2014 |
Visvesh Sathe, Fort Collins, CO US
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20080303552 | Clock Distribution Network Architecture for Resonant-Clocked Systems - Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry. | 12-11-2008 |
20080303576 | Clock Distribution Network Architecture with Resonant Clock Gating - Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal. | 12-11-2008 |
20110215854 | Clock Distribution Network Architecture with Clock Skew Management - Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal. | 09-08-2011 |
20120187991 | CLOCK STRETCHER FOR VOLTAGE DROOP MITIGATION - A clock frequency of a clock signal used by a processor may be temporarily reduced to compensate for voltage droops in the power supply to the processor. A device may include a multiplexer to receive a group of phase shifted versions of the clock signal and to output one of the group of phase shifted versions of the clock signal as an output clock signal. A control component may receive the output clock signal from the multiplexer and a voltage droop event signal indicating whether a voltage droop event is occurring in a power supply. The control component may control, in response to the voltage droop event signal indicating the occurrence of the voltage droop event, the multiplexer to iteratively select the group of phase shifted versions of the clock signal to reduce the frequency of the output clock signal. | 07-26-2012 |
Visvesh S. Sathe, Fort Collins, CO US
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20100072961 | INTERPOSER INCLUDING VOLTAGE REGULATOR AND METHOD THEREFOR - A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device. | 03-25-2010 |
20120154188 | SENSE-AMPLIFIER MONOTIZER - A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase. | 06-21-2012 |
20120161884 | OSCILLATOR DEVICE AND METHODS THEREOF - A signal generator provides a plurality of oscillating signals, whereby each oscillating signal has a different peak voltage and has a predictable and consistent phase relationship with the other oscillating signals. The signal generator includes a plurality of stacked oscillators arranged between two reference voltages, such that each oscillator in the stack generates an oscillating signal having a different peak voltage. Each oscillator stage in a designated oscillator includes a transistor that is connected to a transistor of a corresponding stage in another oscillator. This arrangement of the oscillators provides for charge transfer between the corresponding stages to provide for similar voltage swings in each oscillating signal, as well as to provide for predictable phase relationship between the oscillating signals. | 06-28-2012 |
20140062562 | CONSTRAINING CLOCK SKEW IN A RESONANT CLOCKED SYSTEM - An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected. | 03-06-2014 |
20140062563 | CONTROLLING IMPEDANCE OF A SWITCH USING HIGH IMPEDANCE VOLTAGE SOURCES TO PROVIDE MORE EFFICIENT CLOCKING - A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors. | 03-06-2014 |
20140062564 | PROGRAMMABLE CLOCK DRIVER - A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength. | 03-06-2014 |
20140062565 | CLOCK DRIVER FOR FREQUENCY-SCALABLE SYSTEMS - A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal. | 03-06-2014 |
20140062566 | TRANSITIONING BETWEEN RESONANT CLOCKING MODE AND CONVENTIONAL CLOCKING MODE - A resonant clock network includes an inductor coupled to the clock network through a plurality of switches. When the clock network enters resonant mode, the turn-on of the switches to couple the inductor to the clock network is staggered. The clock network may be formed of multiple regions, each with its own inductor and switches. The turn-on of switches of each region may be staggered with respect to the turn-on off the switches of the other regions as well as to the turn-on of switches within a region. In addition to staggering the turn-on of the switches when entering the resonant mode, the switches may be turned off in a staggered manner when exiting the resonant mode of operation. | 03-06-2014 |