Patent application number | Description | Published |
20110037175 | INTERCONNECTION BETWEEN SUBLITHOGRAPHIC-PITCHED STRUCTURES AND LITHOGRAPHIC-PITCHED STRUCTURES - An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different. | 02-17-2011 |
20110062411 | MOSFET with a Nanowire Channel and Fully Silicided (FUSI) Wrapped Around Gate - Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided. | 03-17-2011 |
20110133161 | Omega Shaped Nanowire Tunnel Field Effect Transistors - A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region. | 06-09-2011 |
20110133162 | Gate-All-Around Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region. | 06-09-2011 |
20110133163 | NANOWIRE FET HAVING INDUCED RADIAL STRAIN - An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire. | 06-09-2011 |
20110133164 | Omega Shaped Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region. | 06-09-2011 |
20110133165 | SELF-ALIGNED CONTACTS FOR NANOWIRE FIELD EFFECT TRANSISTORS - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions. | 06-09-2011 |
20110133166 | NANOWIRE FET HAVING INDUCED RADIAL STRAIN - A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire. | 06-09-2011 |
20110133167 | PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS - A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region. | 06-09-2011 |
20110133169 | Gate-All-Around Nanowire Tunnel Field Effect Transistors - A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region. | 06-09-2011 |
20110168982 | NANOWIRE PIN TUNNEL FIELD EFFECT DEVICES - A method for forming a nanowire tunnel device includes forming a nanowire suspended by a first pad region and a second pad region over a semiconductor substrate, forming a gate structure around a channel region of the nanowire, implanting a first type of ions at a first oblique angle in a first portion of the nanowire and the first pad region, and implanting a second type of ions at a second oblique angle in a second portion of the nanowire and the second pad region. | 07-14-2011 |
20110169051 | Structure for Use in Fabrication of PiN Heterojunction TFET - A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region. | 07-14-2011 |
20120286242 | NANOWIRE PIN TUNNEL FIELD EFFECT DEVICES - A nanowire tunnel device includes a nanowire suspended above a semiconductor substrate by a first pad region and a second pad region, the nanowire having a channel portion surrounded by a gate structure disposed circumferentially around the nanowire, an n-type doped region including a first portion of the nanowire adjacent to the channel portion, and a p-type doped region including a second portion of the nanowire adjacent to the channel portion. | 11-15-2012 |
20120298948 | NANOWIRE FET HAVING INDUCED RADIAL STRAIN - An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire. | 11-29-2012 |
20120298963 | STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET - A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes a silicon wafer comprising an alignment trench, a p-type silicon germanium (SiGe) region, and a hydrogen implantation region underneath the p-type SiGe region and the alignment trench that divides the silicon wafer into a upper silicon region and a lower silicon region, wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and a first oxide layer located over the alignment trench and the p-type SiGe region that fills the alignment trench and is bonded to a second oxide layer located on a handle wafer; wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region. | 11-29-2012 |
20120319084 | PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS - An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer. | 12-20-2012 |