Patent application number | Description | Published |
20090067143 | ELECTRONIC DEVICE HAVING STACK-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure. | 03-12-2009 |
20100038765 | Semiconductor package and method for manufacturing the same - Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically. | 02-18-2010 |
20120021600 | METHOD OF FABRICATING FILM CIRCUIT SUBSTRATE AND METHOD OF FABRICATING CHIP PACKAGE INCLUDING THE SAME - A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area. | 01-26-2012 |
20120199964 | ELECTRONIC DEVICE HAVING STACK-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure. | 08-09-2012 |
20130005088 | METHODS OF FORMING SEMICONDUCTOR MODULES AND SEMICONDUCTOR MODULES FORMED BY THE SAME - Provided are methods of forming semiconductor modules. The method includes forming a high polymer material layer having an adhesive property on a support substrate, adhering a semiconductor chip to the support substrate using the high polymer material layer, bonding the semiconductor chip adhered to the support substrate to a flexible panel, and removing the support substrate. | 01-03-2013 |
20130148312 | TAPE WIRING SUBSTRATE AND CHIP-ON-FILM PACKAGE INCLUDING THE SAME - A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern. | 06-13-2013 |
20130175528 | CHIP ON FILM PACKAGE INCLUDING TEST PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern. | 07-11-2013 |
20130186680 | Tape Film Packages and Methods of Fabricating the Same - A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern. | 07-25-2013 |
20130240917 | SEMICONDUCTOR PACKAGE HAVING A CONDUCTIVE LAYER FOR ELECTROSTATIC DISCHARGE AND DISPLAY DEVICE INCLUDING THE SAME - A semiconductor package is provided. The semiconductor package may include a base film having a first surface and a second surface opposite the first surface, an interconnection pattern on the first surface of the base film, and a ground layer on the second surface of the base film. The semiconductor package may further include a semiconductor chip on the first surface of the base film within the first region and a via contact plug in the second region that penetrates the base film and is configured to electrically connect the interconnection pattern with the ground layer when electrostatic discharge occurs through the via contact plug. | 09-19-2013 |
20130293816 | CHIP-ON-FILM PACKAGE AND DEVICE ASSEMBLY INCLUDING THE SAME - Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate. | 11-07-2013 |
20130344627 | METHOD OF FABRICATING WAFER LEVEL PACKAGE - A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed. | 12-26-2013 |
20140239478 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink. | 08-28-2014 |
20140252605 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. The method of fabricating the semiconductor package includes arranging each of a plurality of second semiconductor chips and each of a plurality of first semiconductor chips to be electrically connected to each other on a first wafer which includes the plurality of first semiconductor chips, with a first width of each of the first semiconductor chips is greater than a second width of each of the second semiconductor chips, forming a first molding layer surrounding the second semiconductor chips on the first wafer, forming a chip package including the first and second semiconductor chips by sawing the first wafer in units of the first semiconductor chips, arranging the chip package on a package substrate to electrically connect the second semiconductor chips to the package substrate, and forming a second molding layer surrounding the chip package on the package substrate. | 09-11-2014 |
20140273350 | METHOD OF FABRICATING SEMICONDUCTOR MULTI-CHIP STACK PACKAGES - Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures. | 09-18-2014 |
20140299980 | SEMICONDUCTOR PACKAGES INCLUDING A HEAT SPREADER AND METHODS OF FORMING THE SAME - Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer. | 10-09-2014 |
20140301055 | PRINTED CIRCUIT BOARD INCLUDING THROUGH REGION AND SEMICONDUCTOR PACKAGE FORMED BY USING THE SAME - Provided is a printed circuit board (PCB). The PCB includes a board body that includes a first surface and a second surface opposite the first surface, a semiconductor chip mounting region that is disposed on the first surface of the board body, and includes a plurality of semiconductor chip mounting parts on which a semiconductor chip may be mounted, a through region that is disposed at a peripheral portion of the semiconductor chip mounting region, and includes a plurality of through holes passing through the board body, and an external terminal forming region that is disposed on the second surface of the board body, wherein a plurality of external terminal forming parts are disposed at the external terminal forming region in correspondence with the respective semiconductor chip mounting parts. | 10-09-2014 |