Patent application number | Description | Published |
20130119338 | RESISTANCE-SWITCHING MEMORY CELLS ADAPTED FOR USE AT LOW VOLTAGE - A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms. Other aspects are also provided. | 05-16-2013 |
20130119510 | DEVICES INCLUDING A P-I-N DIODE DISPOSED ADJACENT A SILICIDE IN SERIES WITH A DIELECTRIC MATERIAL - A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO | 05-16-2013 |
20130121061 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided. | 05-16-2013 |
20130121078 | THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES AND A SINGLE-SIDED WORD LINE ARCHITECTURE - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line. | 05-16-2013 |
20130126821 | BOTTOM ELECTRODES FOR USE WITH METAL OXIDE RESISTIVITY SWITCHING LAYERS - In a first aspect, a metal-insulator-metal (“MIM”) stack is provided that includes a first conductive layer, a resistivity-switching layer having a metal oxide layer formed above the first conductive layer, a material layer between the first conductive layer and the resistivity-switching layer, and a second conductive layer above the resistivity-switching layer. The first conductive layer includes a multi-layer metal-silicide stack, and the material layer has a Gibbs free energy of formation per O between about −3 and −6 eV. A memory cell may be formed from the MIM stack. Numerous other aspects are provided. | 05-23-2013 |
20130130467 | RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES - A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided. | 05-23-2013 |
20130135925 | STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING - A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material. | 05-30-2013 |
20130146832 | MEMORY CELL THAT EMPLOYS A SELECTIVELY GROWN REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - A memory cell is provided that includes a reversible resistance-switching element above a substrate. The reversible resistance-switching element includes an etched material layer that includes an oxidized layer of the etched material layer above a non-oxidized layer of the etched material layer. Numerous other aspects are provided. | 06-13-2013 |
20130148421 | METHODS OF PROGRAMMING TWO TERMINAL MEMORY CELLS - Methods of programming two terminal memory cells are provided. A method includes: (a) reading information of a memory page including first, second, and nth memory cells, the information including first, second, and nth program pulse tuning instructions; (b) creating a first program pulse in accordance with the first program pulse tuning instructions to program the first memory cell; (c) locking the first memory cell from further programming pulses; (d) creating a second program pulse in accordance with the second program pulse tuning instructions to program the second memory cell; (e) locking the second memory cell from further programming pulses; and (f) creating an nth program pulse in accordance with the nth program pulse tuning instructions to program the nth memory cell. | 06-13-2013 |
20130164921 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided. | 06-27-2013 |
20130170283 | LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE - A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode. | 07-04-2013 |
20130175492 | MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME - In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided. | 07-11-2013 |
20130175675 | METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE - A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided. | 07-11-2013 |
20130181181 | MIIIM DIODE HAVING LANTHANUM OXIDE - A MIIIM diode and method of fabricating are disclosed. In one aspect, the MIIIM diode comprises a first metal electrode, a first region comprising a first insulator material having an interface with the first metal electrode, a second region comprising a second insulator material having an interface with the first insulator material, a third region comprising a third insulator material having an interface with the second insulator material, and a second metal electrode having an interface with the third insulator material. At least one of the first, second, or third insulator materials is lanthanum oxide. | 07-18-2013 |
20130183829 | METHODS FOR INCREASED ARRAY FEATURE DENSITY - A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided. | 07-18-2013 |