Patent application number | Description | Published |
20080237599 | MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels. | 10-02-2008 |
20080239787 | LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - An upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium is disclosed. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array. | 10-02-2008 |
20080239790 | METHOD TO FORM A MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A method to form a rewriteable nonvolatile memory cell is disclosed, the cell comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels. | 10-02-2008 |
20080308903 | POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS - A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide. | 12-18-2008 |
20080311710 | METHOD TO FORM LOW-DEFECT POLYCRYSTALLINE SEMICONDUCTOR MATERIAL FOR USE IN A TRANSISTOR - A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors. | 12-18-2008 |
20080311722 | METHOD FOR FORMING POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS - A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide. | 12-18-2008 |
20080315206 | Highly Scalable Thin Film Transistor - Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels. | 12-25-2008 |
20080316795 | Method of making nonvolatile memory device containing carbon or nitrogen doped diode - A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell. | 12-25-2008 |
20080316796 | Method of making high forward current diodes for reverse write 3D cell - A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias. | 12-25-2008 |
20080316808 | Nonvolatile memory device containing carbon or nitrogen doped diode - A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration. | 12-25-2008 |
20080316809 | High forward current diodes for reverse write 3D cell - A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias. | 12-25-2008 |
20080318397 | Junction Diode with Reduced Reverse Current - A method for annealing a diode formed of a silicon-germanium alloy that minimizes leakage current is disclosed. The method includes the steps of forming semiconductor pillars of an alloy of silicon and germanium; heating the pillars at a first temperature for at least 30 minutes, and then heating the pillars at a second temperature higher than the first temperature of the alloy for up to 120 seconds. The invention further includes a monolithic three dimensional memory array of a plurality of p-i-n diodes, the p-i-n diodes being formed of a silicon-germanium alloy that have been subjected to a two-stage heating process. | 12-25-2008 |
20090026582 | DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING - In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above. | 01-29-2009 |
20090085154 | VERTICAL DIODE BASED MEMORY CELLS HAVING A LOWERED PROGRAMMING VOLTAGE AND METHODS OF FORMING THE SAME - In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided. | 04-02-2009 |
20090086521 | MULTIPLE ANTIFUSE MEMORY CELLS AND METHODS TO FORM, PROGRAM, AND SENSE THE SAME - Methods are described to fabricate, program, and sense a multilevel one-time-programmable memory cell including a steering element such as a diode and two, three, or more dielectric antifuses in series. The antifuses may be of different thicknesses, or may be formed of dielectric materials having different dielectric constants, or both. The antifuses and programming pulses are selected such that when the cell is programmed, the largest voltage drop in the memory cell is across only one of the antifuses, while the other antifuses allow some leakage current. In some embodiments, the antifuse with the largest voltage drop breaks down, while the other antifuses remain intact. In this way, the antifuses can be broken down individually, so a memory cell having two, three, or more antifuses may achieve any of three, four, or more unique data states. | 04-02-2009 |
20090179310 | Pillar devices and methods of making thereof - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings. | 07-16-2009 |
20090181515 | Selective germanium deposition for pillar devices - A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device. | 07-16-2009 |
20090194162 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090194163 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090194164 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090197367 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090197368 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090242010 | Method to Form a Photovoltaic Cell Comprising a Thin Lamina Bonded to a Discrete Receiver Element - A donor semiconductor wafer is processed to define a cleave plane, then affixed to a discrete receiver element, which may be glass, metal or a metal compound, plastic, or semiconductor. A semiconductor lamina is cleaved from the donor wafer at the cleave plane. A photovoltaic assembly is fabricated comprising the semiconductor lamina and the receiver element. The photovoltaic assembly comprises a photovoltaic cell. After fabrication, the photovoltaic assembly can be inspected for defects and tested for performance, and select photovoltaic assemblies can be assembled into a completed photovoltaic module. | 10-01-2009 |
20090242031 | Photovoltaic Assembly Including a Conductive Layer Between a Semiconductor Lamina and a Receiver Element - A semiconductor donor body is affixed to a receiver element, and a thin semiconductor lamina is cleaved from the donor body, remaining affixed to the receiver element. A photovoltaic assembly is fabricated which includes the lamina and the receiver element, wherein a photovoltaic cell comprises the lamina. The bond between the semiconductor donor body and the receiver element must survive processing to complete the cell, as well as eventual assembly, transport, and operation in a finished photovoltaic module. It has been found that inclusion of a conductive layer such as titanium or aluminum aids bonding between the semiconductor donor body and the receiver element. In some embodiments, the conductive layer may also serve as an electrical contact and/or as a reflective layer. | 10-01-2009 |
20090261343 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse. | 10-22-2009 |
20090268508 | Reverse leakage reduction and vertical height shrinking of diode with halo doping - One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region. | 10-29-2009 |
20090316468 | LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - A first memory level includes a first plurality of memory cells that includes every memory cell in the first memory level. Each memory cell includes a vertically oriented p-i-n diode in the form of a pillar that includes a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The first plurality of memory cells includes programmed cells and unprogrammed cells, wherein programmed cells comprise at least half of the first plurality of memory cells. Current flowing through the p-i-n diodes of at least 99 percent of the programmed cells when a voltage between about 1.5 volts and about 3.0 volts is applied between the bottom heavily doped p-type region and the top heavily doped n-type region is at least 1.5 microamps. | 12-24-2009 |
20100009488 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 01-14-2010 |
20100031995 | PHOTOVOLTAIC MODULE COMPRISING THIN LAMINAE CONFIGURED TO MITIGATE EFFICIENCY LOSS DUE TO SHUNT FORMATION - A photovoltaic cell can be formed from a thin semiconductor lamina cleaved from a substantially crystalline wafer. Shunts may inadvertently be formed through such a lamina, compromising device performance. By physically severing the lamina into a plurality of segments, the segments of the lamina preferably electrically connected in series, loss of efficiency due to shunt formation may be substantially reduced. In some embodiments, adjacent laminae are connected in series into strings, and the strings are connected in parallel to compensate for the reduction in current caused by severing the lamina into segments. | 02-11-2010 |
20100032010 | METHOD TO MITIGATE SHUNT FORMATION IN A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A photovoltaic cell can be formed from a thin semiconductor lamina cleaved from a substantially crystalline wafer. Shunts may inadvertently be formed through such a lamina, compromising device performance. By physically severing the lamina into a plurality of segments, the segments of the lamina preferably electrically connected in series, loss of efficiency due to shunt formation may be substantially reduced. In some embodiments, adjacent laminae are connected in series into strings, and the strings are connected in parallel to compensate for the reduction in current caused by severing the lamina into segments. | 02-11-2010 |
20100110752 | Method of making a diode read/write memory cell in a programmed state - A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode. | 05-06-2010 |
20100136751 | METHOD FOR MAKING A P-I-N DIODE CRYSTALLIZED ADJACENT TO A SILICIDE IN SERIES WITH A DIELECTRIC ANTIFUSE - A method is described for monolithically forming a first memory level above a substrate, the method including: (a) forming a plurality of first substantially parallel, substantially coplanar conductors above the substrate, the first conductors extending in a first direction; (b) forming a plurality of vertically oriented contiguous p-i-n diodes above the first conductors, the contiguous p-in diode comprising semiconductor material crystallized in contact with a silicide, silicide-germanide, or germanide layer; (c) forming a plurality of second substantially parallel, substantially coplanar conductors, the second conductors above the contiguous p-i-n diodes, the second conductors extending in a second direction different from the first direction, each contiguous p-i-n diode vertically disposed between one of the first conductors and one of the second conductors; (d) and forming a plurality of dielectric rupture antifuses, each dielectric rupture antifuse disposed between one of the contiguous p-i-n diodes and one of the first conductors or between one of the contiguous p-i-n diodes and one of the second conductors, wherein the dielectric rupture antifuses comprise dielectric material, the dielectric material having a dielectric constant greater than about 8. Other aspects are provided. | 06-03-2010 |
20100139755 | FRONT CONNECTED PHOTOVOLTAIC ASSEMBLY AND ASSOCIATED METHODS - A photovoltaic device is disclosed herein that, in various aspects, includes a conductive layer, and a substantially crystalline lamina with a first surface oriented toward the conductive layer and a second surface oriented away from the conductive layer. The lamina thickness is within the range between about 0.2 microns and about 50 microns. An aperture passes through the lamina from the first surface to the second surface. A connector in electrical communication with the conductive layer is disposed through the aperture. Methods of manufacture of the photovoltaic devise are also disclosed. | 06-10-2010 |
20100142255 | METHOD TO PROGRAM A MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided. | 06-10-2010 |
20100154873 | PHOTOVOLTAIC CELL COMPRISING CCONTACT REGIONS DOPED THROUGH LAMINA - In aspects of the present invention, a lamina is formed having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous. | 06-24-2010 |
20100159629 | METHOD TO TEXTURE A LAMINA SURFACE WITHIN A PHOTOVOLTAIC CELL - It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina. | 06-24-2010 |
20100159630 | METHOD FOR MAKING A PHOTOVOLTAIC CELL COMPRISING CONTACT REGIONS DOPED THROUGH A LAMINA - In aspects of the present invention, a method is disclosed to form a lamina having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous. | 06-24-2010 |
20100163831 | DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING - A microelectronic structure including a layerstack is provided, the layerstack including: (a) a first layer including semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, the first layer being between about 50 and 200 angstroms thick, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration; (b) a second layer including semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer includes heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant concentration, the second-layer after-anneal dopant concentration exceeding the second-layer before-anneal concentration; and (c) a third layer including semiconductor material that is above and in contact with the second layer and that is not heavily n-doped before or after being annealed, the third layer having a third-layer dopant concentration. | 07-01-2010 |
20100173457 | Highly scalable thin film transistor - Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels. | 07-08-2010 |
20100177549 | Silicide-silicon oxide-semiconductor antifuse device and method of making - An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer. | 07-15-2010 |
20100181657 | NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE - A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided. | 07-22-2010 |
20100184248 | Creation and Translation of Low-Relieff Texture for a Photovoltaic Cell - Low-relief texture can be created by applying and firing frit paste on a silicon surface. Where frit contacts the surface at high temperature, it etches silicon, dissolving silicon in the softened glass frit. The result is a series of small, randomly located pits, which produce a near-Lambertian surface, suitable for use in a photovoltaic cell. This texturing method consumes little silicon, and is advantageously used in a photovoltaic cell in which a thin silicon lamina comprises the base region of the cell. When the lamina is formed by implanting ions in a donor wafer to form a cleave plane and cleaving the lamina from the donor wafer at the cleave plane, the ion implantation step will serve to translate texture formed at a first surface to the cleave plane, and thus to the second, opposing surface following cleaving. Low-relief texture formed by other methods can be translated from the first surface to the second surface in this way as well. | 07-22-2010 |
20100283053 | NONVOLATILE MEMORY ARRAY COMPRISING SILICON-BASED DIODES FABRICATED AT LOW TEMPERATURE - In embodiments of the invention, a method of forming a monolithic three-dimensional memory array is provided, the method including forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper, and forming a silicon diode in each memory cell, wherein the silicon diode is formed at temperatures compatible with the conductors. The silicon diode may be formed using a hot wire chemical vapor deposition technique, for example. Other aspects are also described. | 11-11-2010 |
20100288996 | MEMORY ARRAYS INCLUDING MEMORY LEVELS THAT SHARE CONDUCTORS, AND METHODS OF FORMING SUCH MEMORY ARRAYS - A memory array is provided that includes a first memory level, a second memory level and a conductor shared between the first and second memory levels. The first memory level includes a first diode and a first resistivity-switching material layer coupled in series with the first diode. The second memory level includes a second diode and a second resistivity-switching material layer coupled in series with the second diode. The first and second resistivity-switching material layers each comprise one or more of Ni | 11-18-2010 |
20100302836 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, Ni | 12-02-2010 |
20100317145 | SELECTIVE ETCH FOR DAMAGE AT EXFFOLIATED SURFACE - Ions are implanted into a silicon donor body, defining a cleave plane. A first surface of the donor body is affixed to a receiver element, and a lamina is exfoliated at the cleave plane, creating a second surface of the lamina. There is damaged silicon at the second surface, which will compromise the efficiency of a photovoltaic cell formed from the lamina. A selective etchant, having an etch rate which is positively correlated with the concentration of structural defects in silicon, is used to remove the damaged silicon at the second surface, while removing very little of the relatively undamaged lamina. | 12-16-2010 |
20110049466 | LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - A memory is provided that includes a first memory level having a plurality of memory cells. Each memory cell includes a vertically oriented p-i-n diode including a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided. | 03-03-2011 |
20110076796 | INTERMETAL STACK FOR USE IN A PHOTOVOLTAIC CELL - A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a transparent conductive oxide layer serving as a quarter-wave plate, a low resistance layer, an adhesion layer to help adhesion to the receiver element, and may also include a barrier layer to prevent or impede unwanted diffusion within the stack. | 03-31-2011 |
20110114913 | HETEROJUNCTION DEVICE COMPRISING A SEMICONDUCTOR AND A RESISTIVITY-SWITCHING OXIDE OR NITRIDE - In the present invention, a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor. For example, a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array. | 05-19-2011 |
20110136326 | PILLAR DEVICES AND METHODS OF MAKING THEREOF - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings. | 06-09-2011 |
20110176352 | NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL - A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate. | 07-21-2011 |
20110186797 | MEMORY CELL THAT INCLUDES A SIDEWALL COLLAR FOR PILLAR ISOLATION AND METHODS OF FORMING THE SAME - In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided. | 08-04-2011 |
20110210305 | METHOD TO PROGRAM A MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided. | 09-01-2011 |
20110266514 | MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided. | 11-03-2011 |
20110287615 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse. | 11-24-2011 |
20110318911 | NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE - A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF | 12-29-2011 |
20120001296 | P-I-N DIODE CRYSTALLIZED ADJACENT TO A SILICIDE IN SERIES WITH A DIELECTRIC MATERIAL - A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided. | 01-05-2012 |
20120012808 | DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING - A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb | 01-19-2012 |
20120056147 | LARGE ARRAY OF UPWARD POINTINIG P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode is coupled to a resistivity-switching element and includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided. | 03-08-2012 |
20120205655 | METHOD TO TEXTURE A LAMINA SURFACE WITHIN A PHOTOVOLTAIC CELL - It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina. | 08-16-2012 |
20120208317 | Intermetal Stack for Use in a Photovoltaic Cell - A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a transparent conductive oxide layer serving as a quarter-wave plate, a low resistance layer, an adhesion layer to help adhesion to the receiver element, and may also include a barrier layer to prevent or impede unwanted diffusion within the stack. | 08-16-2012 |
20120280202 | HETEROJUNCTION DEVICE COMPRISING A SEMICONDUCTOR AND A RESISTIVITY-SWITCHING OXIDE OR NITRIDE - A monolithic three dimensional memory array is provided that includes a first memory level formed above a substrate, and a second memory level monolithically formed above the first memory level. The first memory level includes a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction, a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction, the second direction different from the first direction, the second conductors above the first conductors, and a first plurality of devices. Each of the first plurality of devices is disposed between one of the first conductors and one of the second conductors, and includes a resistivity-switching binary metal oxide or nitride compound and a silicon, germanium, or silicon-germanium alloy resistor of a single conductivity type. Numerous other aspects are provided. | 11-08-2012 |
20120300533 | NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL - A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided. | 11-29-2012 |
20130320287 | MEMORY CELL THAT EMPLOYS A SELECTIVELY GROWN REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided. | 12-05-2013 |