| Patent application number | Description | Published |
|---|
| 20150194427 | SEMICONDUCTOR DEVICES INCLUDING FINFETS AND LOCAL INTERCONNECT LAYERS AND METHODS OF FABRICATING THE SAME - Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a finFET, a metal routing layer, a first local interconnect layer, and a second local interconnect layer. The finFET may include a channel, a first source/drain region, a second source/drain region, and a gate stack. The metal routing layer may be separated from the finFET in a vertical direction. The first local interconnect layer may include a first local interconnect that contacts a first metal route in the metal routing layer and that electrically connects to the first source/drain region. The second local interconnect layer may include a second local interconnect that contacts a second metal route in the metal routing layer and that electrically connects to the gate stack. | 07-09-2015 |
| 20150318355 | METHODS OF FORMING DEFECT-FREE SRB ONTO LATTICE-MISMATCHED SUBSTRATES AND DEFECT-FREE FINS ON INSULATORS - A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures. | 11-05-2015 |
| 20150364542 | Integrated Circuits with Si and Non-Si Nanosheet FET Co-Integration with Low Band-to-Band Tunneling and Methods of Fabricating the Same - An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs. | 12-17-2015 |
| 20150364546 | NANOSHEET FETS WITH STACKED NANOSHEETS HAVING SMALLER HORIZONTAL SPACING THAN VERTICAL SPACING FOR LARGE EFFECTIVE WIDTH - A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance. | 12-17-2015 |
| 20160071848 | SEMICONDUCTOR DEVICE WITH AN ISOLATION GATE AND METHOD OF FORMING - An embodiment includes a semiconductor device, comprising: a substrate; a continuous diffusion region disposed on the substrate; a first gate structure disposed on the continuous diffusion region; a second gate structure disposed on the continuous diffusion region; an isolation gate structure disposed between the first gate structure and the second gate structure and disposed adjacent to the both the first gate structure and the second gate structure; a first diffusion region of the continuous diffusion region disposed between the first gate structure and the isolation gate structure; a second diffusion region of the continuous diffusion region disposed between the second gate structure and the isolation gate structure; a conductive layer disposed on the first and second diffusion regions; and an isolation gate contact disposed over the isolation gate structure and electrically insulated from the first diffusion region. | 03-10-2016 |
| 20160104787 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE CONTACTS ON SOURCE/DRAINS - Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer. | 04-14-2016 |
| 20160111421 | MULTIPLE CPP FOR INCREASED SOURCE/DRAIN AREA FOR FETS INCLUDING IN A CRITICAL SPEED PATH - An integrated circuit comprises at least one block comprising a first cell and a second cell. The first cell comprises a first FET formed with a first contacted poly pitch (CPP), and the second cell comprises a second FET formed with a second CPP. The first CPP is greater than the second CPP. The first FET is part of a critical-speed path, and the second FET is part of a noncritical-speed path, in which the critical-speed path operates at a faster speed than the noncritical-speed path. The first FET and the second FET each comprise a planar FET, a finFET, a gate-all-around FET or a nanosheet FET. A method for forming the integrated circuit is also disclosed. | 04-21-2016 |
| 20160133513 | METAL OXYSILICATE DIFFUSION BARRIERS FOR DAMASCENE METALLIZATION WITH LOW RC DELAYS AND METHODS FOR FORMING THE SAME - A method is disclosed to form a metal-oxysilicate diffusion barrier for a damascene metallization. A trench is formed in an Inter Layer Dielectric (ILD) material. An oxysilicate formation-enhancement layer comprising silicon, carbon, oxygen, a constituent component of the ILD, or a combination thereof, is formed in the trench. A barrier seed layer is formed on the oxysilicate formation-enhancement layer comprising an elemental metal selected from a first group of elemental metals in combination with an elemental metal selected from a second group of elemental metals. An elemental metal in the second group is immiscible in copper or an alloy thereof, has a diffusion constant greater than a self-diffusion of copper or an alloy thereof; does not reducing silicon-oxygen bonds during oxysilicate formation; and promotes adhesion of copper or an alloy of copper to the metal-oxysilicate barrier diffusion layer. The structure is then annealed to form a metal-oxysilicate diffusion barrier. | 05-12-2016 |
