Patent application number | Description | Published |
20080246015 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 10-09-2008 |
20090017593 | METHOD FOR SHALLOW TRENCH ISOLATION - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 01-15-2009 |
20100173452 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 07-08-2010 |
20110186960 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 08-04-2011 |
20110186992 | RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed. | 08-04-2011 |
20110186998 | RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed. | 08-04-2011 |
20120319231 | Microelectronic Device Including Shallow Trench Isolation Structures Having Rounded Bottom Surfaces - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 12-20-2012 |
20140080285 | METHOD AND APPARATUS FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES HAVING ROUNDED CORNERS - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 03-20-2014 |
20140103452 | ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES - In an embodiment, an apparatus includes a substrate including a surface having a planar portion and a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate. The apparatus also includes a first transistor that includes a first gate region formed over the fin feature, a first source region formed from a body of the fin feature, and a first drain region formed from the body of the fin feature. Additionally, the apparatus includes a second transistor that includes a second gate region formed over the fin feature, a second source region formed from the body of the fin feature, and a second drain region formed from the body of the fin feature. Further, the apparatus includes an isolation component formed between the first transistor and the second transistor, where the isolation component has a width less than 30 nm. | 04-17-2014 |
20140104924 | APPARATUS AND METHOD FOR REPAIRING RESISTIVE MEMORIES AND INCREASING OVERALL READ SENSITIVITY OF SENSE AMPLIFIERS - A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch. | 04-17-2014 |
20140104926 | SYSTEMS AND METHODS FOR READING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS - A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage. A comparator compares a second voltage on the bit line to a third voltage supplied to the comparator and generates an output based on the comparison. A latch latches the output of the comparator and generates a latched output. A pulse generator generates a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output. The latched output indicates a state of the resistive random access memory cell. | 04-17-2014 |
20140104927 | CONFIGURING RESISTIVE RANDOM ACCESS MEMORY (RRAM) ARRAY FOR WRITE OPERATIONS - A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line. The driver circuit is configured to apply, in response to selection of the resistive random access memory cell using the word line, a first voltage of a first polarity to the bit line to program the resistive random access memory cell to a first state by causing current to flow through the resistive element in a first direction, and a second voltage of a second polarity to the bit line to program the resistive random access memory cell to a second state by causing current to flow through the resistive element in a second direction. | 04-17-2014 |
20140104928 | METHOD AND APPARATUS FOR FORMING A CONTACT IN A CELL OF A RESISTIVE RANDOM ACCESS MEMORY TO REDUCE A VOLTAGE REQUIRED TO PROGRAM THE CELL - A cell of a resistive random access memory including a resistive element and an access device. The resistive element includes (i) a first electrode and (ii) a second electrode. The access device is configured to select and deselect the cell. The access device includes (i) a first terminal connected to a first contact and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact includes (i) a first surface in contact with the second contact and (ii) a second surface in contact with the second electrode. The first surface defines a first surface area, and the second surface defines a second surface area. The first surface area is greater than the second surface area. | 04-17-2014 |
20140112057 | APPARATUS AND METHOD FOR REFORMING RESISTIVE MEMORY CELLS - A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell. | 04-24-2014 |
20140124961 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 05-08-2014 |
20140170832 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR CONTROLLING MANUFACTURING OF CORRESPONDING SUB-RESOLUTION FEATURES OF CONDUCTIVE AND RESISTIVE ELEMENTS - A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory. | 06-19-2014 |
20150063004 | METHOD AND APPARATUS FOR REFORMING A MEMORY CELL OF A MEMORY - A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle. | 03-05-2015 |