Patent application number | Description | Published |
20080304327 | Methods and apparatuses for refreshing non-volatile memory - Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells. | 12-11-2008 |
20090052269 | Charge loss compensation methods and apparatus - Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis. | 02-26-2009 |
20090084838 | STACK POSITION LOCATION IDENTIFICATION FOR MEMORY STACKED PACKAGES - A method for use with devices in a stacked package is disclosed. By preprogramming a unique identifier into a device during manufacture, the device can determine its position in the stack and perform a task based on its position in the stack. In one embodiment, the task is power-up. | 04-02-2009 |
20100039860 | MEMORY DEVICES AND METHODS OF STORING DATA ON A MEMORY DEVICE - Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells. | 02-18-2010 |
20110199826 | CHARGE LOSS COMPENSATION METHODS AND APPARATUS - Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis. | 08-18-2011 |
20120275221 | MEMORY DEVICES AND METHODS OF STORING DATA ON A MEMORY DEVICE - Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells. | 11-01-2012 |
20140293697 | CHARGE LOSS COMPENSATION METHODS AND APPARATUS - Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis. | 10-02-2014 |
Patent application number | Description | Published |
20110080787 | NON-VOLATILE MEMORY APPARATUS AND METHODS - Some embodiments include apparatus and methods having memory cells coupled in series and a module to cause an application of voltages with at least three different values to gates of the memory cells during an operation to retrieve information stored in at least one of the memory cells. Additional apparatus and methods are described. | 04-07-2011 |
20110080789 | AUTOMATIC SELECTIVE SLOW PROGRAM CONVERGENCE - Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described. | 04-07-2011 |
20110107014 | MEMORY DEVICE PAGE BUFFER CONFIGURATION AND METHODS - Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time. | 05-05-2011 |
20110280082 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described. | 11-17-2011 |
20110310664 | NON-VOLATILE MEMORY APPARATUS AND METHODS - Some embodiments include apparatus and methods having memory cells coupled in series and a module to cause an application of voltages with at least three different values to gates of the memory cells during an operation to retrieve information stored in at least one of the memory cells. Additional apparatus and methods are described. | 12-22-2011 |
20120254699 | DYNAMIC READ CHANNEL CALIBRATION FOR NON-VOLATILE MEMORY DEVICES - Embodiments of the invention describe a dynamic read reference voltage for use in reading data from non-volatile memory cells. In embodiments of the invention, the read reference voltage is calibrated as the non-volatile memory device is used. Embodiments of the invention may comprise of logic and or modules to read data from a plurality of non-volatile memory cells using a first read reference voltage level (e.g., an initial read reference voltage level whose value is determined by the non-volatile device manufacturer). An Error Checking and Correction (ECC) algorithm is performed to identify whether errors exist in the data as read using the first read reference voltage level. If errors in the data as read are identified, a pre-determined value is retrieved to adjust the first read reference voltage level to a second read reference voltage level. | 10-04-2012 |
20120300549 | MEMORY DEVICE PAGE BUFFER CONFIGURATION AND METHODS - Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time. | 11-29-2012 |
20130073786 | APPARATUS, SYSTEM, AND METHOD FOR IMPROVING READ ENDURANCE FOR A NON-VOLATILE MEMORY - Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB. | 03-21-2013 |
20130215680 | AUTOMATIC SELECTIVE SLOW PROGRAM CONVERGENCE - Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described. | 08-22-2013 |
20130223153 | NON-VOLATILE MEMORY APPARATUS AND METHODS - Some embodiments include apparatus and methods having memory cells coupled in series and a module to cause an application of voltages with at least three different values to gates of the memory cells during an operation to retrieve information stored in at least one of the memory cells. Additional apparatus and methods are described. | 08-29-2013 |
20130268726 | Dual Mode Write Non-Volatile Memory System - Host writes may be handled differently from background writes to non-volatile memory systems. As a result of using different write algorithms for host writes and backgrounds writes, maximum system lifetime and the maximum system performance may be improved in some embodiments. | 10-10-2013 |
20130286743 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described. | 10-31-2013 |
20140047302 | CYCLING ENDURANCE EXTENDING FOR MEMORY CELLS OF A NON-VOLATILE MEMORY ARRAY - Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program. | 02-13-2014 |
20140281203 | MANAGING DISTURBANCE INDUCED ERRORS - In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells. | 09-18-2014 |
20140321205 | MEMORY DEVICE PAGE BUFFER CONFIGURATION AND METHODS - Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time. | 10-30-2014 |
20150046611 | DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT - Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system. | 02-12-2015 |
20150248937 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described. | 09-03-2015 |
Patent application number | Description | Published |
20090079520 | ACOUSTICALLY COUPLED RESONATORS HAVING RESONANT TRANSMISSION MINIMA - A bandpass filter includes input and output terminals, first and second acoustic resonators, and an acoustic coupling layer. The first acoustic resonator includes first and second electrodes, and a piezoelectric layer between the first and second electrodes. The first electrode of the first acoustic resonator is connected to the input terminal. The second acoustic resonator includes first and second electrodes, and a piezoelectric layer between the first and second electrodes. The acoustic coupling is provided between the second electrode of the first acoustic resonator and the first electrode of the second acoustic resonator. The output terminal is connected to the second electrode of the second acoustic resonator. A capacitor extends between the input terminal and the output terminal. The filter's frequency response includes at least two transmission zeros. | 03-26-2009 |
20100096745 | BONDED WAFER STRUCTURE AND METHOD OF FABRICATION - A method of packaging electronics comprises providing a first wafer and providing a second wafer. The method also comprises depositing a polymer material over a surface of the first wafer; and selectively removing a portion of the polymer from the first wafer to create a void in the polymer. The method also comprises placing the first wafer over the second wafer and in contact with the polymer; and curing the polymer to bond the first wafer to the second wafer. A bonded wafer structure is also described. | 04-22-2010 |
20150145610 | PACKAGED DEVICE WITH ACOUSTIC RESONATOR AND ELECTRONIC CIRCUITRY AND METHOD OF MAKING THE SAME - A device includes: a base substrate having a bonding pad and a peripheral pad, the peripheral pad encompassing the bonding pad; an acoustic resonator on the base substrate; a cap substrate having a bonding pad seal and a peripheral pad seal, the bonding pad seal bonding around the perimeter of the bonding pad and the peripheral pad seal bonding with the peripheral pad to define a sealed volume between the cap substrate and the base substrate, the cap substrate having a through hole therein over the bonding pad providing access for a connection to the bonding pad; a low-resistivity material layer region disposed on a portion of a surface of the cap substrate disposed inside the sealed volume, the material layer region being isolated from the bonding pad seal; and electronic circuitry disposed in the material layer region and electrical connected with the acoustic resonator. | 05-28-2015 |
20150215111 | LOW JITTER DEVICE AND SYSTEM - A communication apparatus includes a serializer transmission circuit (TX) configured to receive a plurality of data channels in parallel, and the serializer transmission circuit (TX) transmits data serially as a data stream signal. A film bulk acoustic resonator (FBAR) is coupled with the serializer transmission circuit (TX). The film bulk acoustic resonator is part of an ultra-low phase noise reference oscillator configured to generate an ultra-high frequency reference clock signal. | 07-30-2015 |