Rozario
Daniel Sylvester Rozario, Kanata CA
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20140006078 | WORKFLOW MANAGEMENT AND TASK TRACKING | 01-02-2014 |
Deborah Anne Rozario, Hathern GB
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20120097164 | APPARATUSES AND METHODS FOR POSITIVE EXPIRATORY PRESSURE THERAPY - A positive expiratory pressure device (PEP) has one or more of the following features, alone or in any combination: 1) a combination of oscillation PEP therapy and standard PEP therapy, 2) use of microwavable materials, 3) use of an oscillation rocker that produces a venturi effect, 4) use of a flexible tube to create the air pressure oscillation, 5) use of a rotating wheel to open and close the air channel and create air pressure oscillation, 6) use of a variable cross section air channel to generate different air flow resistance for providing multiple levels of constant pressure therapy, 7) use of a flexible air flow stopper plate with adjustable pivot point to generate different air flow resistance for providing multiple levels of constant pressure therapy, and 8) use of a selection switch that allows the device to switch between standard PEP therapy and oscillatory PEP therapy. | 04-26-2012 |
Lisa V. Rozario, San Jose, CA US
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20090206865 | ELECTRICAL TEST STRUCTURE AND METHOD FOR CHARACTERIZATION OF DEEP TRENCH SIDEWALL RELIABILITY - A test structure and testing method are provided for characterizing the time-dependent drift in the parasitic PFET leakage current that flows along the sidewall of a deep trench isolation structure from the P-type active area to the P-type substrate in a semiconductor integrated circuit structure. The capacitive coupling characteristics of the deep trench isolation structure are used to control the electrical “bias” of the deep trench structure through the use of a large auxiliary trench mesh network that is formed as part of the deep trench structure. The trench mesh network can be placed adjacent to a Vdd ring or a ground ring and then, by using a ratioed capacitive voltage dividing network, the electrical potential at the trench can be controlled. | 08-20-2009 |
Louis-Raymond Rozario, Singapore SG
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20090200278 | LASER WELDING SYSTEM - A laser welding system includes a free-spacing beam delivery laser head having a linear array of at least two laser diodes. Each of the diodes generates a laser beam of a predetermined wavelength and spectral width, the laser beams adapted to weld a workpiece having a first component and at least one other component to be welded to the first component, the first component being substantially transmissive to the wavelength, the other component being substantially absorptive of the wavelength. A lens is spaced a predetermined distance from each of the laser diodes, each of the lenses adapted to focus the respective laser beam into a focused laser beam segment, thereby forming a continuous line of laser energy from a substantially serial combination of each focused laser beam segment. The continuous line of laser energy is in a plane containing the workpiece, and is substantially orthogonal to the workpiece translation direction. | 08-13-2009 |
Novellone Rozario, Yardville, NJ US
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20160065400 | ADAPTIVE LINEARIZER - An adaptive linearizer system includes an adaptive linearizer circuit that is configured to pre-distort an input signal based on one or more control signals to generate a pre-distorted signal, and a non-linear high-power amplifier (HPA) having non-linear characteristics that is coupled to the adaptive linearizer circuit. The nonlinear HPA amplifies the pre-distorted signal. The pre-distortion characteristics of the adaptive linearizer circuit provide for countering the non-linear characteristics of the non-linear HPA and compensating a non-linearity of the non-linear HPA. | 03-03-2016 |
Novellone Rozario, Trenton, NJ US
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20160056881 | MULTI-STAGE LINEARIZER - A high-linearity linearizer system includes a multi-stage linearizer circuit formed by cascading multiple linearizer circuits. The multi-stage linearizer circuit is configured to pre-distort an input signal to generate a pre-distorted signal. A non-linear high-power amplifier (HPA) having non-linear characteristics is coupled to the multi-stage linearizer circuit and is configured to amplify the pre-distorted signal. Pre-distortion characteristics of the multi-stage linearizer circuit are configured to counter the non-linear characteristics of the non-linear HPA and to compensate a non-linearity of the non-linear HPA to achieve a desired level of linearity. | 02-25-2016 |
Ranjit Rozario, San Jose, CA US
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20100278190 | HIERARCHICAL PIPELINED DISTRIBUTED SCHEDULING TRAFFIC MANAGER - A hierarchical pipelined distributed scheduling traffic manager includes multiple hierarchical levels to perform hierarchical winner selection and propagation in a pipeline including selecting and propagating winner queues of a lower level to subsequent levels to determine one final winning queue. The winner selection and propagation is performed in parallel between the levels to reduce the time required in selecting the final winning queue. In some embodiments, the hierarchical traffic manager is separated into multiple separate sliced hierarchical traffic managers to distributively process the traffic. | 11-04-2010 |
20120170472 | ON-CHIP PACKET CUT-THROUGH - Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor. | 07-05-2012 |
Ranjit J. Rozario, Sunnyvale, CA US
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20150067384 | Crossing Pipelined Data between Circuitry in Different Clock Domains - An integrated circuit implements a multistage processing pipeline, where control is passed in the pipeline with data to be processed according to the control. At least some of the different pipeline stages can be implemented by different circuits, being clocked at different frequencies. These frequencies may change dynamically during operation of the integrated circuit. Control and data to be processed according to such control can be offset from each other in the pipeline; e.g., control can precede data by a pre-set number of clock events. To cross a clock domain, control and data can be temporarily stored in respective FIFOs. Reading of control by the destination domain is delayed by a delay amount determined so that reading of control and data can be offset from each other by a minimum number of clock events of the destination domain clock, and control is read before data is available for reading. | 03-05-2015 |
Ranjit J. Rozario, San Jose, CA US
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20120079228 | DIGITAL COUNTER SEGMENTED INTO SHORT AND LONG ACCESS TIME MEMORY - A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated. | 03-29-2012 |
20150242212 | MODELESS INSTRUCTION EXECUTION WITH 64/32-BIT ADDRESSING - In an aspect, a processor supports modeless execution of 64 bit and 32 bit instructions. A Load/Store Unit (LSU) decodes an instruction that without explicit opcode data indicating whether the instruction is to operate in a 32 or 64 bit memory address space. LSU treats the instruction either as a 32 or 64 bit instruction in dependence on values in an upper 32 bits of one or more 64 bit operands supplied to create an effective address in memory. In an example, a 4 GB space addressed by 32-bit memory space is divided between upper and lower portions of a 64-bit address space, such that a 32-bit instruction is differentiated from a 64-bit instruction in dependence on whether an upper 32 bits of one or more operands is either all binary 1 or all binary 0. Such a processor may support decoding of different arithmetic instructions for 32-bit and 64-bit operations. | 08-27-2015 |
20150242274 | PIPELINED ECC-PROTECTED MEMORY ACCESS - In one aspect, a pipelined ECC-protected cache access method and apparatus provides that during a normal operating mode, for a given cache transaction, a tag comparison action and a data RAM read are performed speculatively in a time during which an ECC calculation occurs. If a correctable error occurs, the tag comparison action and data RAM are repeated and an error mode is entered. Subsequent transactions are processed by performing the ECC calculation, without concurrent speculative actions, and a tag comparison and read are performed using only the tag data available after the ECC calculation. A reset to normal mode is effected by detecting a gap between transactions that is sufficient to avoid a conflict for use of tag comparison circuitry for an earlier transaction having a repeated tag comparison and a later transaction having a speculative tag comparison. | 08-27-2015 |
20160055083 | PROCESSORS AND METHODS FOR CACHE SPARING STORES - In one aspect, a processor has a register file, a private Level 1 (L1) cache, and an interface to a shared memory hierarchy (e.g., an Level 2 (L2) cache and so on). The processor has a Load Store Unit (LSU) that handles decoded load and store instructions. The processor may support out of order and multi-threaded execution. As store instructions arrive at the LSU for processing, the LSU determines whether a counter, from a set of counters, is allocated to a cache line affected by each store. If not, the LSU allocates a counter. If so, then the LSU updates the counter. Also, in response to a store instruction, affecting a cache line neighboring a cache line that has a counter that meets a criteria, the LSU characterizes that store instruction as one to be effected without obtaining ownership of the effected cache line, and provides that store to be serviced by an element of the shared memory hierarchy. | 02-25-2016 |
Ranjit Joseph Rozario, San Jose, CA US
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20120331265 | Apparatus and Method for Accelerated Hardware Page Table Walk - A method of walking page tables includes comparing a virtual address to a plurality of virtual address bit segments to identify a match. Each virtual address bit segment is associated with a page table level that has a page table base address. A designated page table base address is received in response to the match. The page table walk starts at the designated page table, thereby skipping over earlier page tables. | 12-27-2012 |
20130263124 | Apparatus and Method for Guest and Root Register Sharing in a Virtual Machine - A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources. | 10-03-2013 |
20140068138 | Embedded Processor with Virtualized Security Controls Using Guest Identifications, a Common Kernel Address Space and Operational Permissions - A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection. | 03-06-2014 |
20160077866 | EMBEDDED PROCESSOR WITH VIRTUALIZED SECURITY CONTROLS USING GUEST IDENTIFICATIONS, A COMMON KERNEL ADDRESS SPACE AND OPERATIONAL PERMISSIONS - A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection. | 03-17-2016 |
Robert P. Rozario, San Jose, CA US
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20150317473 | DEVICE AND ACCESSORY PAIRING - A device authenticates accessories by detecting that an accessory is attached to the device, determining a unique identification (ID) for the accessory, determining, based on the unique ID, if the accessory has been paired to the device, and in response to determining that the accessory has been paired to the device, enable use of the accessory by the device. In response to determining the accessory has not been paired to the device, the devices performs a secondary authentication process on the accessory. | 11-05-2015 |
20160003911 | BATTERY CELL CHARACTERISTIC IDENTIFICATION - Devices, systems, and methods for battery monitoring are disclosed. An example method performs a first measurement on a battery cell installed in a location to determine a first charging capacity and determines a set of values for a permitted charging capacity trace region based on the first charging capacity and a number of charge/discharge cycles subsequent to performing the first measurement. The example method performs a second measurement on a battery cell installed in the location to determine a second charging capacity and compares the second charging capacity to the permitted charging capacity trace region and determines that the battery cell installed in the location at a time of the second measurement is not the same battery cell installed in the location at the time of the first measurement when the second charging capacity is not a value within the set of permitted values of the charging capacity trace region. | 01-07-2016 |
Savio Rozario, Columbus, OH US
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20120286526 | STRIKER STIFFENER REINFORCEMENT - A striker reinforcement plate for support of a striker member on an automotive vehicle body. The plate has a first substantially planar face, including at least two holes for receiving mating bolts or screws. A flange extends from multiple edges of the face substantially perpendicular to the face. The flange includes mounting tabs extending outwardly and substantially perpendicular to the flange. The mounting tabs are provided for mating with an automotive vehicle pillar. The face of the striker reinforcement plate mates with a rear surface of a striker stiffener. | 11-15-2012 |