Patent application number | Description | Published |
20080220606 | SELF-ALIGNED METAL TO FORM CONTACTS TO Ge CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY - A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate. | 09-11-2008 |
20080227259 | SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs - A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device. | 09-18-2008 |
20080227283 | SELF-ALIGNED METAL TO FORM CONTACTS TO Ge CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY - A method for forming gennano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate. | 09-18-2008 |
20080246120 | REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SiGe CONTAINING SUBSTRATES - A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided. | 10-09-2008 |
20080290142 | METHOD AND PROCESS FOR REDUCING UNDERCOOLING IN A LEAD-FREE TIN-RICH SOLDER ALLOY - Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition. | 11-27-2008 |
20080299720 | STABILIZATION OF Ni MONOSILICIDE THIN FILMS IN CMOS DEVICES USING IMPLANTATION OF IONS BEFORE SILICIDATION - A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used. | 12-04-2008 |
20100155456 | METHOD AND PROCESS FOR REDUCING UNDERCOOLING IN A LEAD-FREE TIN-RICH SOLDER ALLOY - Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition. | 06-24-2010 |
20110162702 | QUASI-PYRAMIDAL TEXTURED SURFACES USING PHASE-SEGREGATED MASKS - A method of texturing a surface of a substrate utilizing a phase-segregated mask and etching is disclosed. The resulting textured surface, which can be used as a component of a solar cell includes, in one embodiment, a randomly mixed collection of flat-topped and angled surfaces providing local high points and local low points. The flat-topped surfaces have an areal density of at least 1%, and the high points are coincident with the flat-topped surfaces. Moreover, a preponderance of said low points are approximately situated in a single common plane parallel to the plane defined by the flat-topped surfaces. | 07-07-2011 |
20110206934 | GRAPHENE FORMATION UTILIZING SOLID PHASE CARBON SOURCES - A method for forming a single, few-layer, or multi-layer graphene and structure is described incorporating selecting a substrate having a buried layer of carbon underneath a metal layer, providing an ambient and providing a heat treatment to pass carbon through the metal layer to form a graphene layer on the metal layer surface or incorporating a metal-carbon layer which is heated to segregate carbon in the form of graphene to the surface or chemically reacting the metal in the metal-carbon layer with a substrate containing Si driving the carbon to the surface whereby graphene is formed. | 08-25-2011 |
20110256675 | SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs - A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device. | 10-20-2011 |