Patent application number | Description | Published |
20120029712 | SYSTEMS, METHODS AND APPARATUS FOR INDEXING AND PREDICTING WIND POWER OUTPUT FROM VIRTUAL WIND FARMS - This disclosure describes systems, methods, and apparatus for predicting electrical power output from wind farms using statistical methods and measured wind speeds near boundaries of control volumes that encompass the wind turbines of interest. These systems, methods, and apparatus can provide electrical power output predictions of up to 6, 12, 24, or 48 hours in advance of actual power reaching the grid. | 02-02-2012 |
20130060472 | SYSTEMS, METHODS AND APPARATUS FOR INDEXING AND PREDICTING WIND POWER OUTPUT FROM VIRTUAL WIND FARMS - This disclosure describes systems, methods, and apparatus for predicting electrical power output from wind farms using statistical methods and measured wind speeds near boundaries of control volumes that encompass the wind turbines of interest. These systems, methods, and apparatus can provide electrical power output predictions of up to 6, 12, 24, or 48 hours in advance of actual power reaching the grid. | 03-07-2013 |
Patent application number | Description | Published |
20090215747 | HETEROCYCLIC COMPOUNDS AS INHIBITORS OF BETA-LACTAMASES - This invention discloses and claims methods for inhibiting bacterial β-lactamases and treating bacterial infections by inhibiting bacterial β-lactamases in man or an animal comprising administering a therapeutically effective amount to said man or said animal of a compound, or pharmaceutically acceptable salt thereof, of formula (I) either alone or in combination with a β-lactamine antibiotic wherein said combination can be administered separately, together or spaced out over time. Pharmaceutical compositions comprising a compound of formula (I), or a combination of a compound of formula (I) and a therapeutically effective amount of a β-lactamine antibiotic, and a pharmaceutically acceptable carrier are also disclosed and claimed. | 08-27-2009 |
20100048528 | HETEROCYCLIC COMPOUNDS AS INHIBITORS OF BETA-LACTAMASES - This invention discloses and claims methods for inhibiting bacterial β-lactamases and treating bacterial infections by inhibiting bacterial β-lactamases in man or an animal comprising administering a therapeutically effective amount to said man or said animal of a compound, or pharmaceutically acceptable salt thereof, of formula (I) either alone or in combination with a β-lactamine antibiotic wherein said combination can be administered separately, together or spaced out over time. Pharmaceutical compositions comprising a compound of formula (I), or a combination of a compound of formula (I) and a therapeutically effective amount of a β-lactamine antibiotic, and a pharmaceutically acceptable carrier are also disclosed and claimed. | 02-25-2010 |
20110021772 | New heterocyclic compounds, their preparation and their use as medicaments, in particular as anti-bacterial agents - The invention relates to new heterocyclic compounds of general formula (I), and their salts with a base or an acid: | 01-27-2011 |
20110213147 | New heterocyclic compounds, their preparation and their use as medicaments, in particular as anti-bacterial agents - The invention relates to new heterocyclic compounds of general formula (I), and their salts with a base or an acid: | 09-01-2011 |
20110245254 | HETEROCYCLIC COMPOUNDS AS INHIBITORS OF BETA-LACTAMASES - This invention discloses and claims methods for inhibiting bacterial β-lactamases and treating bacterial infections by inhibiting bacterial β-lactamases in man or an animal comprising administering a therapeutically effective amount to said man or said animal of a compound, or pharmaceutically acceptable salt thereof, of formula (I) either alone or in combination with a β-lactamine antibiotic wherein said combination can be administered separately, together or spaced out over time. Pharmaceutical compositions comprising a compound of formula (I), or a combination of a compound of formula (I) and a therapeutically effective amount of a β-lactamine antibiotic, and a pharmaceutically acceptable carrier are also disclosed and claimed. | 10-06-2011 |
Patent application number | Description | Published |
20100227151 | POLYURETHANE FOAM - A method of making a polyurethane foam from a mixture of isocyanate modified polyol and foam-forming ingredients, wherein the isocyanate modified polyol is made by reacting at least one polyol with at least one multifunctional isocyanate, wherein the isocyanate modified polyol is a non-foamed polyol polymer having available OH groups, wherein the foam forming ingredients comprise at least a multifunctional isocyanate and a foaming agent, preferably water, and characterised in that (i) the at least one polyol from which the isocyanate modified polyol is made comprises at least one lipid-based polyol which has undergone reaction with the isocyanate in the presence of a PU gelation catalyst, and/or (ii) the isocyanate modified polyol is mixed with a lipid-based polyol prior to, or at the same time as, foaming. | 09-09-2010 |
20140329923 | POLYURETHANE FOAM - A method of making a polyurethane foam from a mixture of isocyanate modified polyol and foam-forming ingredients, wherein the isocyanate modified polyol is made by reacting at least one polyol with at least one multifunctional isocyanate, wherein the isocyanate modified polyol is a non-foamed polyol polymer having available OH groups, wherein the foam forming ingredients comprise at least a multifunctional isocyanate and a foaming agent, preferably water, and characterised in that (i) the at least one polyol from which the isocyanate modified polyol is made comprises at least one lipid-based polyol which has undergone reaction with the isocyanate in the presence of a PU gelation catalyst, and/or (ii) the isocyanate modified polyol is mixed with a lipid-based polyol prior to, or at the same time as, foaming. | 11-06-2014 |
20140336347 | METHOD OF REDUCING ODORS OF LIPID-BASED POLYOLS - A method of reducing odors in lipid-based polyol. At least one lipid-based polyol is provided, and mixed with ricinoleic acid and/or a metal salt of ricinoleic acid. Isocyanate may be added, preferably toluene diisocyanate (TDI). The polyol, and the isocyanate when present, are reacted in the presence of the ricinoleic acid and/or a metal salt of ricinoleic acid which reduces or removes odors in the lipid-based polyol. When isocyanate is used, low, limiting levels are preferred, well below the level required to fully react with all of the polyol. Tin, zinc, sodium, and calcium ricinoleic acid metal salts are particularly preferred. Preferably the reaction takes place without added heat, at room temperature. The reaction may be performed in a chamber which is under at least a partial vacuum. | 11-13-2014 |
Patent application number | Description | Published |
20150043575 | SUPPORTING MULTICAST IN NOC INTERCONNECT - Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the NoC during routing towards the destination components indicated in the message. Example implementations further relate to an efficient way of implementing multicast in any given NoC topology, wherein one or more multicast trees in the given NoC topology are formed and one of these trees are used for routing a multicast message to its intended destination components mentioned therein. | 02-12-2015 |
20150052309 | COMBINING ASSOCIATIVITY AND CUCKOO HASHING - Addition, search, and performance of other allied activities relating to keys are performed in a hardware hash table. Further, high performance and efficient design may be provided for a hash table applicable to CPU caches and cache coherence directories. Set-associative tables and cuckoo hashing are combined for construction of a directory table of a directory based cache coherence controller. A method may allow configuration of C cuckoo ways, where C is an integer greater than or equal to 2, wherein each cuckoo way C | 02-19-2015 |
20150103822 | NOC INTERFACE PROTOCOL ADAPTIVE TO VARIED HOST INTERFACE PROTOCOLS - Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that support a variety of different component protocols each having different sets of data and/or metadata even after the NoC is designed and finalized. Example implementations include, automatically changing format of packets received from an originating SoC component by an originating bridge based on a NoC interface protocol and then transmitting the packet across the NoC interconnect to a destination bridge. The format may again be changed based on the protocol of the destination SoC component. The proposed protocol can be configured to map various transactions presented to it, be they packets belonging to the physical, data link layer, network layer or transport layer. As part of the mapping process, virtual channels for latency or deadlock avoidance may be created and may be maintained for the entire life of the packet within the NoC. | 04-16-2015 |
20150143050 | REUSE OF DIRECTORY ENTRIES FOR HOLDING STATE INFORMATION - The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory. | 05-21-2015 |
20150186277 | CACHE COHERENT NOC WITH FLEXIBLE NUMBER OF CORES, I/O DEVICES, DIRECTORY STRUCTURE AND COHERENCY POINTS - The present application is directed to designing a NoC interconnect architecture by a means of specification, which can indicate implementation parameters of the NoC including, but not limited to, number of NoC agent interfaces, and number of cache coherency controllers. Flexible identification of NoC agent interfaces and cache coherency controllers allows for an arbitrary number of agents to be associated with the NoC upon configuring the NoC from the specification. | 07-02-2015 |
20150324288 | SYSTEM AND METHOD FOR IMPROVING SNOOP PERFORMANCE - The present disclosure is directed to hardware hash tables, and more specifically, to generation of a cache coherent system such as in a Network on Chip (NoC). The present disclosure is further directed to a directory structure that includes a new field, referred to, for instance as, encoded value, which indicates the original owner of a dirty line. As an original holder may have held or modified the original line, by tracking the original holder, example implementations can track the agents that are potentially dirty, as the encoded value can indicate the agent with the most recently unique line, which can then be shared with the other agents. | 11-12-2015 |
20150370720 | USING CUCKOO MOVEMENT FOR IMPROVED CACHE COHERENCY - Example implementations of the present disclosure are directed to handling the eviction of a conflicting cuckoo entry while reducing performance degradation resulting. In example implementations, when an address is replacing another address, the evicted address does not necessarily map to the same places as the new address. Example implementations attempt to conduct a run through of the cache coherent directory with the new entry such that the evicted address can find an empty entry in the directory and fill the empty entry. | 12-24-2015 |
Patent application number | Description | Published |
20140177648 | TAGGING AND SYNCHRONIZATION FOR FAIRNESS IN NOC INTERCONNECTS - Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve tagging the messages with meta-information when the messages are injected in the interconnection network. Example implementations may involve routers using various arbitration phases, and making local arbitration decisions based on the meta-information of incoming messages. The meta-information can be of various types based on the number of router arbitration phases, and the desired level of sophistication. | 06-26-2014 |
20140204735 | AUTOMATIC DEADLOCK DETECTION AND AVOIDANCE IN A SYSTEM INTERCONNECT BY CAPTURING INTERNAL DEPENDENCIES OF IP CORES USING HIGH LEVEL SPECIFICATION - Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips. | 07-24-2014 |
20140204764 | QOS IN HETEROGENEOUS NOC BY ASSIGNING WEIGHTS TO NOC NODE CHANNELS AND USING WEIGHTED ARBITRATION AT NOC NODES - Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations. | 07-24-2014 |
20140211622 | CREATING MULTIPLE NOC LAYERS FOR ISOLATION OR AVOIDING NOC TRAFFIC CONGESTION - Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem. | 07-31-2014 |
20140376569 | MULTIPLE CLOCK DOMAINS IN NOC - Example implementations described herein are directed to a micro-architecture of NoC router clocking which allows for a flexible Globally Asynchronous Locally Synchronous (GALS) implementation. The example implementations allow arbitrary clock domain partitions to be defined across the system. The example implementations further involve allowing the components of the NoC to be configured by the user through a NoC generation system to achieve the desired arbitrary clock domain partitioning. | 12-25-2014 |
20150016257 | IDENTIFICATION OF INTERNAL DEPENDENCIES WITHIN SYSTEM COMPONENTS FOR EVALUATING POTENTIAL PROTOCOL LEVEL DEADLOCKS - Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve automatically generating internal dependency specification of a system component based on dependencies between incoming/input and outgoing/output interface channels of the component. Dependencies between incoming and outgoing interface channels of the component can be determined by blocking one or more outgoing interface channels and evaluating impact of the blocked outgoing channels on the incoming interface channels. Another implementation described herein involves determining inter-component communication dependencies by measuring impact of a deadlock on the blocked incoming interface channels of one or more components to identify whether a dependency cycle is formed by blocked incoming interface channels. | 01-15-2015 |
Patent application number | Description | Published |
20120069288 | LIQUID CRYSTAL POLYMER LAYER FOR ENCAPSULATION AND IMPROVED HERMITICITY OF CIRCUITIZED SUBSTRATES - A substrate and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of polytetrafluoroethylene (PTFE) placed upon both sides of the CIC. A layer of etched copper foil is placed on the outer surface of each PTFE layer. A layer of liquid crystal polymer (LCP) is placed on both layers of etched copper foil. An external layer of etched copper foil is placed on the external surface of the LCP layers. | 03-22-2012 |
20130196550 | DIFFERENTIALLY COUPLED CONNECTOR - A connector is provided with a pair of terminals configured to provide a differential signal pair. A ground terminal is positioned on opposing sides of the differential pair. The body of the differential pair is configured so as to bring the differential pair closer together. In an embodiment, the % coupling on the differential pair is increase at least 10% more than a design where the four terminals are positioned at a constant pitch between the tail and the contact. | 08-01-2013 |
20150140861 | HIGH DENSITY CONNECTOR - A connector can be provided that allows for improved route-out including straight-back routing. Signal and ground terminal tails can be arranged in a single row to help facilitate such functionality. Consequentially, a connector with two vertically stacked card slots can be provided that allows for straight back routing of the signal traces in four layers while still providing a compact connector design. | 05-21-2015 |
20150295358 | DIFFERENTIALLY COUPLED CONNECTOR - A connector is provided with a pair of terminals configured to provide a differential signal pair. A ground terminal is positioned on opposing sides of the differential pair. The body of the differential pair is configured so as to bring the differential pair closer together. In an embodiment, the % coupling on the differential pair is increase at least 10% more than a design where the four terminals are positioned at a constant pitch between the tail and the contact. | 10-15-2015 |
20160036147 | HIGH DENSITY CONNECTOR - A connector can be provided that allows for improved route-out including straight-back routing. Signal and ground terminal tails can be arranged in a single row to help facilitate such functionality. A commoning member can connect ground tails to ground terminals. Consequentially, a connector with two vertically stacked card slots can be provided that allows for straight back routing of the signal traces in four layers while still providing a compact connector design. | 02-04-2016 |
Patent application number | Description | Published |
20090300282 | REDUNDANT ARRAY OF INDEPENDENT DISKS WRITE RECOVERY SYSTEM - A redundant array of independent disks write recovery system includes: providing a logical drive having a disk drive that failed; rebooting a storage controller, coupled to the disk drive, after a controller error; and reading a write hole table, in the storage controller, for regenerating data on the logical drive. | 12-03-2009 |
20120047548 | NETWORK STORAGE SYSTEM WITH DATA PREFETCH AND METHOD OF OPERATION THEREOF - A method of operation of a network storage system includes: receiving a host command for displaying a video stream; performing a forced read ahead of the video stream beyond the host command including: identifying a high definition video stream, dynamically setting a block count and a loop count for the forced read ahead, and transferring data from hard disk drives to a cache for anticipating a host next command; and transferring cached data from the cache for responding to the host next command for displaying the video stream. | 02-23-2012 |
20120297135 | REDUNDANT ARRAY OF INDEPENDENT DISKS SYSTEM WITH INTER-CONTROLLER COMMUNICATION AND METHOD OF OPERATION THEREOF - A method of operation of a redundant array of independent disks system includes: instantiating a first controller having a first local map and a first remote map; instantiating a second controller having a second local map and a second remote map mapped to the first local map; mapping a first memory device to the first local map by the first controller; coupling a storage device to the second controller and the first controller; and switching control of the storage device to the first controller, when a failure of the second controller is detected, by the first controller reading the first memory device. | 11-22-2012 |
20130198563 | DISK STORAGE SYSTEM WITH REBUILD SEQUENCE AND METHOD OF OPERATION THEREOF - A method of operation of a disk storage system includes: providing a disk storage controller; coupling a first physical disk to the disk storage controller; detecting a failure of the first physical disk; and rebuilding a first logical drive, after replacing the first physical disk, including: selecting a selected stripe of the first logical drive, detecting a selected stripe status of the selected stripe, and marking the selected stripe as on-line in the selected stripe status. | 08-01-2013 |