Patent application number | Description | Published |
20100259239 | REGULATOR CONTROL CIRCUITS, SWITCHING REGULATORS, SYSTEMS, AND METHODS FOR OPERATING SWITCHING REGULATORS - A regulator control circuit includes a high side driver that is configured to receive a supply voltage. A capacitor is configured to store charges. A first transistor is coupled between the capacitor at a first node and a gate of a high side driver at a second node. The first node is capable of being boosted to a voltage to operate the first transistor at a saturation mode for a charge sharing between the first node and the second node so as to substantially turn on the high side driver. | 10-14-2010 |
20110187566 | NOISE SHAPING FOR DIGITAL PULSE-WIDTH MODULATORS - A noise shaper that compares an input signal to a feedback output signal, which is a truncated version of the input signal, and generates the difference between the two signals (i.e., the error). The noise shaper then integrates the errors by adding to the error multiple of its delayed versions, and quantizes the integrated errors in such a way that the spectrum of the quantization noise is shaped toward high frequencies to be removed by a LC low-pass filter used in conjunction with the noise shaper. The low frequency content of the desired signal is mostly unaffected. | 08-04-2011 |
20120038340 | DYNAMIC CONTROL LOOP FOR SWITCHING REGULATORS - Some embodiments regard a method of controlling a regulator having an input voltage and an output voltage, comprising: turning on a first driver; determining a duration ratio having a first time period over the first time period and a second time period; the first time period and the second time period indicating a duration when the first driver and a second driver is on, respectively; generating a second voltage level for the reference voltage based on the duration ratio and a ripple voltage that is a difference between a high threshold voltage and a low threshold voltage; turning off the first driver and turning on the second driver based on a relationship between the second voltage level and a voltage level of the output voltage; turning off the second driver when a current flowing through a node of the output voltage reaches a pre-determined level; and generating a change in the first time period based on the duration ratio and a voltage difference between a peak of the output voltage and the high threshold voltage. | 02-16-2012 |
20120056659 | INTEGRATED CIRCUITS FOR CONVERTING A HIGH VOLTAGE LEVEL TO A LOW VOLTAGE LEVEL - An integrated circuit includes a high side driver and a low side driver. The low side driver is electrically coupled with the high side driver. A circuit is electrically coupled with the high side driver and a first node between the high side driver and the low side driver. The circuit is configured to substantially turn off the high side driver if the high side driver leaves a cutoff region of the high side driver during a tri-state mode. | 03-08-2012 |
20120133345 | HYSTERETIC POWER CONVERTER WITH CALIBRATION CIRCUIT - A hysteretic power converter includes a comparator, a calibration circuit, and an output node having an output voltage. The calibration circuit is configured to supply a calibrated voltage to the comparator. The comparator controls the output voltage based on the calibrated voltage and a feedback voltage representing at least a portion of the output voltage. | 05-31-2012 |
20120146716 | Apparatus for Controlling Slew Rate - An apparatus for controlling slew rate is coupled to two adjustable voltage rails. The output of the apparatus is coupled to the gate of a switching element. By employing two adjustable voltage rails, the slew rate of the switching element is proportional to the voltage difference between the first adjustable rail and the second adjustable rail. The slew rate control apparatus can be applied to a variety of switching elements including N channel Field Effect Transistors (NFETs), P channel Field Effect Transistors (PFETs), current mode logic circuits and level shifter circuits. | 06-14-2012 |
20120194141 | Battery Charger Digital Control Circuit and Method - A digital controlled battery charger comprises a power converter, a voltage sensor, a current senor, a mode selector and a digital controller. The voltage sensor and current sensor detect the voltage of a rechargeable battery and the current flowing through the rechargeable battery respectively. The mode selector selects a feedback signal from either the output of the voltage sensor or the output of the current sensor. The digital controller receives the selected feedback signal and generates a pulse width modulated signal for the power converter. Additionally, the digital controller is capable of dynamically adjusting its coefficients so that the control loop can maintain a stable system when the battery charger operates in different battery charging phases. | 08-02-2012 |
20120235728 | Level Shifter Design - A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V | 09-20-2012 |
20130009795 | NOISE SHAPING FOR DIGITAL PULSE-WIDTH MODULATORS - A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output. | 01-10-2013 |
20130058049 | PACKAGE SYSTEMS INCLUDING PASSIVE ELECTRICAL COMPONENTS - A package system includes at least one active circuitry disposed over a substrate. A passivation structure is disposed over the at least one active circuitry. The passivation structure has at least one opening that is configured to expose at least one first electrical pad. At least one passive electrical component is disposed over the passivation structure. The at least one passive electrical component is electrically coupled with the at least one first electrical pad. | 03-07-2013 |
20130082668 | SINGLE-INDUCTOR MULTIPLE-OUTPUT DC TO DC CONVERTER - A DC to DC converter includes a switching circuit and a controller. The switching circuit includes an inductor coupled to first and second voltage supply nodes and to a plurality of output loads. The controller is configured to monitor a current through the inductor and to selectively couple the inductor to each of the plurality of output loads such that at least one of the following criteria is met: 1) an average current through the inductor is minimized for the particular output loads coupled to the switching circuit, or 2) minimize a number of times the switching circuit is switched during a charging period for the particular output loads coupled to the switching circuit. | 04-04-2013 |
20130119511 | INDUCTOR HAVING BOND-WIRE AND MANUFACTURING METHOD THEREOF - The present application discloses an inductor including a substrate, a first conductive line and a second conductive line formed over the substrate, a passivation layer formed over the first and the second conductive lines, and a bond wire coupling an end of the first conductive line and an end of the second conductive line. At least a portion of the at least one bond wire is positioned above an upper surface of the passivation layer. The first conductive line, the bond wire, and the second conductive line are connected to form a coil. | 05-16-2013 |
20130135131 | IDLE TONE SUPPRESSION CIRCUIT - A hysteretic digital filter includes a first multi-bit flip-flop having an input for receiving a series of multi-bit sigma-delta ADC codes, a clock input for receiving a clock signal and an output; a second multi-bit flip-flop having an input coupled to the output of the first multi-bit flip-flop, an output for providing an output code of the digital filter, and an input for receiving a latch control signal, the second multi-bit flip-flop latching its input to its output under control of the latch control signal; and a control circuit. The control circuit is configured to selectively provide the latch control signal to trigger latching by the second multi-bit flip-flop dependent on a running comparison of the output code of the digital filter and the value of individual ones of the multi-bit sigma-delta ADC codes from the series of multi-bit sigma-delta ADC codes. | 05-30-2013 |
20130135782 | VARIABLE PRECISION THERMAL SENSOR - A high accuracy on-chip thermal sensor includes an integrated circuit and sensing elements. The thermal sensor finds application in various mobile and battery powered devices and includes a processor that analyzes a measured temperature signal and decides if the thermal sensor operates in low or high power operational mode, or if the device's CPU is to be reset. A method utilizing the thermal sensor includes making comparisons to two threshold temperatures and operating at low power mode below the first threshold temperature, high power mode between the two threshold temperatures and causing reset if the second threshold temperature is exceeded. Low power operational mode includes a lower clock frequency, lower bias current and lower power consumption. Higher power operational mode is used when the upper threshold temperature is being approached and includes a higher data sampling frequency and more accurate temperature control and uses higher power. | 05-30-2013 |
20130136149 | TEMPERATURE SENSOR WITH DIGITAL TRIM AND TRIMMING METHOD THEREOF - A method for calibrating a temperature sensor comprises: receiving first and second reference voltages from respective first and second tap points within a string of sequentially connected resistive devices of the temperature sensor. Each resistive device has a resistance that varies as a function of temperature. The receiving is performed at two or more known temperatures. A respective code is output corresponding to each respective one of the two or more known temperatures, based on the first and second reference voltages. At least one of the tap points is adjusted, based on the two or more known temperatures and the respective output codes. | 05-30-2013 |
20130241510 | DYNAMIC CONTROL LOOP FOR SWITCHING REGULATORS - In accordance with an embodiment, a regulator includes a controller, a driving unit, a digital-to-analog converter, and a comparator. The controller is configured to output a digital reference voltage and to output a control signal responsive to a comparison signal. The driving unit is configured to generate an output voltage at a first node responsive to the control signal. The digital-to-analog converter is configured to generate an analog reference voltage responsive to the digital reference voltage. The comparator is configured to generate the comparison signal based on the analog reference voltage and the output voltage. | 09-19-2013 |
20130241599 | COMPARATOR CIRCUIT HAVING A CALIBRATION CIRCUIT - A comparator has a first terminal, a second terminal, and an output terminal. A selection circuit is coupled to the first terminal. A calibration circuit is coupled to the output terminal and the second terminal. The comparator is configured to operate in a first mode when the selection circuit provides a first input signal to the first terminal and the calibration circuit provides a second input signal to the second terminal. The comparator is configured to operate in a second mode when the selection circuit provides a first calibration signal to the first terminal and the calibration circuit provides a second calibration signal to the second terminal based on an output signal at the output terminal. The comparator generates the output signal based on the first calibration signal and the second calibration signal. | 09-19-2013 |
20130307510 | METHOD FOR CONVERTING A HIGH VOLTAGE LEVEL TO A LOW VOLTAGE LEVEL - In a method, a high voltage level is converted to a low voltage level by using a high side driver and a low side driver electrically coupled with the high side driver. The high side driver is substantially turned off upon a detection that the high side driver leaves a cutoff region of the high side driver during a tri-state mode. | 11-21-2013 |
20130307663 | RESISTOR ARRANGEMENT AND METHOD OF USE - This disclosure relates to a semiconductor device including resistor arrangement including a first resistor electrically connected to a ground voltage and a second resistor in direct physical contact with the first resistor. The second resistor is configured to receive a temperature independent current and the second resistor has thermal properties similar to those of the first resistor. This disclosure also relates to a semiconductor device including a load configured to receive an operating voltage and a voltage source configured to supply the operating voltage. The semiconductor device further includes a resistor arrangement between the load and the voltage source. This disclosure also relates to a method of using a resistor arrangement to calculate an operating current. | 11-21-2013 |
20140002041 | DIGITAL LOW DROP-OUT REGULATOR | 01-02-2014 |
20140211905 | RATIO METER OF A THERMAL SENSOR - A ratio meter includes a converter circuit, a first counter, a delay circuit, and a second counter. The converter circuit is configured to receive a temperature-independent signal, to convert the received temperature-independent signal into a first frequency signal during a first phase, to receive a temperature-dependent signal, and to convert the temperature-dependent signal into a second frequency signal during a second phase. The first counter is configured to receive the first frequency signal and to generate a control signal by counting a predetermined number of pulses of the first frequency signal count. The delay circuit is configured to delay the control signal for a predetermined time delay. The second counter is configured to receive the second frequency signal and to generate a count value by counting the second frequency signal. | 07-31-2014 |
20140266097 | METHOD FOR CONVERTING A HIGH VOLTAGE LEVEL TO A LOW VOLTAGE LEVEL - An integrated circuit for converting a high voltage level to a low voltage level comprises a high side driver, a low side driver electrically coupled with the high side driver, a circuit electrically coupled with the high side driver and a first node between the high side driver and the low side driver, and a false signal filter electrically coupled with the circuit. The circuit is configured to substantially turn off the high side driver if the high side driver leaves a cutoff region of the high side driver during a tri-state mode. The false signal filter is configured to screen signals that are outside of the tri-state mode. | 09-18-2014 |
20140269839 | THERMAL SENSOR WITH TEMPERATURE CONTROL - In a thermal sensor. a capacitor voltage of a capacitor is compared with a reference voltage, and an output voltage is generated based on the comparison. The output voltage has a pulse density indicative of a temperature detected by the thermal sensor. The capacitor is charged or discharged using at least one of a first current signal or a second current signal based on a logic level of the output voltage. The first current signal is a temperature-independent signal, and the second current signal is a temperature-dependent signal dependent on the temperature detected by the thermal sensor. In some embodiments, a clock rate of a clock signal is varied in accordance with the detected temperature to control a timing operation for supplying the first current signal to the capacitor and/or the reference voltage is varied in accordance with the detected temperature. | 09-18-2014 |
20150077078 | SELF-ADJUSTING REGULATOR AND METHOD OF USING SAME - A self-adjusting regulator includes a power stage adjusting an output voltage and a control loop for controlling the power stage. The control loop includes a compensator adjusting a bandwidth in response to at least one compensator control signal, and an oscillator controlling a switching speed in response to at least one oscillator control signal. The self-adjusting regulator further includes a voltage sensing control circuit controlling the control loop. The voltage sensing control circuit generating the at least one compensator control signal and the at least one oscillator control signal based on a comparison of the output voltage and a reference voltage. In a low speed mode, the compensator outputs a first bandwidth, and the oscillator outputs a first switching speed. In a high speed mode, the compensator outputs a second bandwidth greater than the first bandwidth, and the oscillator outputs a second switching speed faster than the first switching speed. | 03-19-2015 |
Patent application number | Description | Published |
20100018353 | APPARATUS AND METHODS TO MANUFACTURE PDC BITS - A method to manufacture a drill bit including constructing a bit head portion of the drill bit, constructing a bit shank portion of the drill bit, aligning the bit head portion with the bit shank portion, and electron beam welding a butted joint between the bit head portion and the bit shank portion. | 01-28-2010 |
20100038407 | METHODS OF HARDBANDING JOINTS OF PIPE USING FRICTION STIR WELDING - A method for applying a wear reducing material to a tool used in a wellbore operation that includes welding a hardfacing alloy to a surface of the tool, wherein the welding comprises friction stirring the alloy into the tool's surface is disclosed. Methods of welding a preformed sleeve or width of wear reducing material using friction stirring are also disclosed. | 02-18-2010 |
20100038408 | METHODS OF TREATING HARDBANDED JOINTS OF PIPE USING FRICTION STIR PROCESSING - A method for treating a wear reducing material welded to a surface of a tool used in a wellbore operation that includes friction stirring the wear reducing material into the surface of the tool is disclosed. Method for improving the properties of a wear reducing material on a tool are also disclosed. | 02-18-2010 |
20100071961 | BIT LEG OUTER SURFACE PROCESSING USING FRICTION STIR WELDING (FSW) - A roller cone drill bit includes a bit body and at least one leg extending downward from the bit body. Each leg includes an outer surface, a ball hole plug located in the outer surface, a shoulder, a shirttail, and a roller cone rotatably mounted to the leg. The outer surface of each leg is surface processed by friction stirring. | 03-25-2010 |
20100078224 | BALL HOLE WELDING USING THE FRICTION STIR WELDING (FSW) PROCESS - A roller cone drill bit includes a bit body, at least one leg extending downward from the bit body, a journal on each leg, and a roller cone mounted on each journal. A ball race is configured between each journal and roller cone, and a plurality of retention balls is disposed within each ball race. A ball hole extends from the back face of each leg to the ball race, and a ball hole plug fits within the ball hole. The ball hole plug is secured to the leg by a friction stir weld. | 04-01-2010 |
20140034394 | BALL HOLE WELDING USING THE FRICTION STIR WELDING (FSW) PROCESS - A roller cone drill bit includes a bit body, at least one leg extending downward from the bit body, a journal on each leg, and a roller cone mounted on each journal. A ball race is configured between each journal and roller cone, and a plurality of retention balls is disposed within each ball race. A ball hole extends from the back face of each leg to the ball race, and a ball hole plug fits within the ball hole. The ball hole plug is secured to the leg by a friction stir weld. | 02-06-2014 |
20140374156 | METHODS OF REDUCING STRESS IN DOWNHOLE TOOLS - A method for reducing stress in a downhole tool. The method includes varying a temperature of the downhole tool by at least 5° C. Vibrational energy may be transferred to the downhole tool with a vibration device coupled to the downhole tool. The vibrational energy may cause the downhole tool to move with a frequency from about 10 Hz to about 5 kHz. | 12-25-2014 |
Patent application number | Description | Published |
20090023207 | CHROMOSOME 3p21.3 GENES ARE TUMOR SUPPRESSORS - Tumor suppressor genes play a major role in the pathogenesis of human lung cancer and other cancers. Cytogenetic and allelotyping studies of fresh tumor and tumor-derived cell lines showed that cytogenetic changes and allele loss on the short arm of chromosome 3 (3p) are most frequently involved in about 90% of small cell lung cancers and greater than 50% of non-small cell lung cancers. A group of recessive oncogenes, Fus1, 101F6, Gene 21 (NPRL2), Gene 26 (CACNA2D2), Luca 1 (HYAL1), Luca 2 (HYAL2), PL6, 123F2 (RaSSFI), SEM A3 and Beta* (BLU), as defined by homozygous deletions in lung cancers, have been located and isolated at 3p21.3. | 01-22-2009 |
20120076851 | CHROMOSOME 3p21.3 GENES ARE TUMOR SUPPRESSORS - Tumor suppressor genes play a major role in the pathogenesis of human lung cancer and other cancers. Cytogenetic and allelotyping studies of fresh tumor and tumor-derived cell lines showed that cytogenetic changes and allele loss on the short arm of chromosome 3 (3p) are most frequently involved in about 90% of small cell lung cancers and greater than 50% of non-small cell lung cancers. A group of recessive oncogenes, Fus1, 101F6, Gene 21 (NPRL2), Gene 26 (CACNA2D2), Luca 1 (HYAL1), Luca 2 (HYAL2), PL6, 123F2 (RaSSFI), SEM A3 and Beta* (BLU), as defined by homozygous deletions in lung cancers, have been located and isolated at 3p21.3. | 03-29-2012 |
20120108880 | CHROMOSOME 3p21.3 GENES ARE TUMOR SUPPRESSORS - Tumor suppressor genes play a major role in the pathogenesis of human lung cancer and other cancers. Cytogenetic and allelotyping studies of fresh tumor and tumor-derived cell lines showed that cytogenetic changes and allele loss on the short arm of chromosome 3 (3p) are most frequently involved in about 90% of small cell lung cancers and greater than 50% of non-small cell lung cancers. A group of recessive oncogenes, Fus1, 101F6, Gene 21 (NPRL2), Gene 26 (CACNA2D2), Luca 1 (HYAL1), Luca 2 (HYAL2), PL6, 123F2 (RaSSFI), SEM A3 and Beta* (BLU), as defined by homozygous deletions in lung cancers, have been located and isolated at 3p21.3. | 05-03-2012 |
20140377339 | TUSC2 THERAPIES - A method for predicting a subject's response to a TUSC2 therapy is provided. In particular, a subject's response is predicted based on the proportion of cancers cells that are apoptotic. Also provided is a method of treating a subject previously predicted to have a favorable response with a TUSC2 therapy. Methods for treating cancer by administration of a TUSC2 therapeutic in conjunction with an EGFR inhibitor and/or a protein kinase inhibitor are also disclosed. Kits and reagents for use in TUSC2 therapy are provided. | 12-25-2014 |
Patent application number | Description | Published |
20090192746 | Methods for Altering One or More Parameters of a Measurement System - Methods for altering one or more parameters of a measurement system are provided. One method includes analyzing a sample using the system to generate values from classification channels of the system for a population of particles in the sample. The method also includes identifying a region in a classification space in which the values for the populations are located. In addition, the method includes determining an optimized classification region for the population using one or more properties of the region. The optimized classification region contains a predetermined percentage of the values for the population. The optimized classification region is used for classification of particles in additional samples. | 07-30-2009 |
20090237658 | Methods for Altering One or More Parameters of a Measurement System - Methods for altering one or more parameters of a measurement system are provided. One method includes analyzing a sample using the system to generate values from classification channels of the system for a population of particles in the sample. The method also includes identifying a region in a classification space in which the values for the populations are located. In addition, the method includes determining an optimized classification region for the population using one or more properties of the region. The optimized classification region contains a predetermined percentage of the values for the population. The optimized classification region is used for classification of particles in additional samples. | 09-24-2009 |
20100017358 | Methods, Storage Mediums, and Systems for Configuring Classification Regions Within a Classification Matrix of an Analysis System and for Classifying Particles of an Assay - Methods and systems are provided which include configurations for the reassigning unit locations of a classification matrix at which two or more classification regions overlap as non-classification regions. In addition, methods and systems are provided which include configurations for mathematically creating classification regions which may be characterized by values which more accurately correspond to measured values of particles. Other embodiments of methods and systems include configurations for acquiring data corresponding to measurable parameters of a particle and identifying a location within a classification matrix to which at least some of the data corresponds. Such methods and systems further include configurations for translating either the data corresponding to the identified unit location or a target space located at known locations within the classification matrix a preset number of predetermined coordinate paths until a conclusion that the particle may be classified to particular particle category or a reject class is attained. | 01-21-2010 |
20100228513 | Systems and Methods for Performing Measurements of One or More Materials - Systems and methods for performing measurements of one or more materials are provided. One system is configured to transfer one or more materials to an imaging volume of a measurement device from one or more storage vessels. Another system is configured to image one or more materials in an imaging volume of a measurement device. An additional system is configured to substantially immobilize one or more materials in an imaging volume of a measurement device. A further system is configured to transfer one or more materials to an imaging volume of a measurement device from one or more storage vessels, to image the one or more materials in the imaging volume, to substantially immobilize the one or more materials in the imaging volume, or some combination thereof. | 09-09-2010 |
20100241360 | Methods, Data Structures, and Systems for Classifying Microparticles - Methods, data structures, and systems for classifying particles are provided. In particular, the methods and systems are configured to acquire a first set of data corresponding to measurable parameters of a microparticle and identify a location of a look-up table to which the first set of data corresponds, wherein the look-up table is framed by values associated with at least one of the measurable parameters. Furthermore, the methods and systems are configured to determine whether the first set of data fits one or more predefined algorithms respectively indicative of a different microparticle classification associated with the identified location of the look-up table. The methods and systems are further configured to classifying the microparticle within at least one predefined categorization based upon the determination of whether the first set of data fits the one or more predefined algorithms. | 09-23-2010 |
20110106495 | Methods for Altering One or More Parameters of a Measurement System - Methods for altering one or more parameters of a measurement system are provided. One method includes analyzing a sample using the system to generate values from classification channels of the system for a population of particles in the sample. The method also includes identifying a region in a classification space in which the values for the populations are located. In addition, the method includes determining an optimized classification region for the population using one or more properties of the region. The optimized classification region contains a predetermined percentage of the values for the population. The optimized classification region is used for classification of particles in additional samples. | 05-05-2011 |
20120002875 | Methods and Systems for Image Data Processing - Methods, storage mediums, and systems for image data processing are provided. Embodiments for the methods, storage mediums, and systems include configurations to perform one or more of the following steps: background signal measurement, particle identification using classification dye emission and cluster rejection, inter-image alignment, inter-image particle correlation, fluorescence integration of reporter emission, and image plane normalization. | 01-05-2012 |
20120002882 | Methods and Systems for Image Data Processing - Methods, storage mediums, and systems for image data processing are provided. Embodiments for the methods, storage mediums, and systems include configurations to perform one or more of the following steps: background signal measurement, particle identification using classification dye emission and cluster rejection, inter-image alignment, inter-image particle correlation, fluorescence integration of reporter emission, and image plane normalization. | 01-05-2012 |
20120008869 | Methods and Systems for Image Data Processing - Methods, storage mediums, and systems for image data processing are provided. Embodiments for the methods, storage mediums, and systems include configurations to perform one or more of the following steps: background signal measurement, particle identification using classification dye emission and cluster rejection, inter-image alignment, inter-image particle correlation, fluorescence integration of reporter emission, and image plane normalization. | 01-12-2012 |
20120028366 | FLOW CYTOMETER AND FLUIDIC LINE ASSEMBLY WITH MULTIPLE INJECTION NEEDLES - A flow cytometer is provided which includes an interrogation flow cell and a plurality of assay fluidic lines extending into the interrogation flow cell. A method of operating such a flow cytometer includes priming the interrogation flow cell with a sheath fluid and injecting different assay fluids into a flow of the sheath fluid through the plurality of fluidic lines. A fluidic line assembly is provided which includes a plurality of capillary tubes coupled to a base section configured for coupling to an interrogation flow cell assembly of a flow cytometer. The capillary tubes are dimensionally configured such that when the fluidic line assembly is arranged within the flow cytometer and fluid is dispensed from one or more of the capillary tubes at a given pressure differential with respect to an encompassing sheath fluid within the interrogation flow cell the fluid is substantially centrally aligned within the interrogation flow cell. | 02-02-2012 |
20130022502 | Systems and Methods for Performing Measurements of One or More Materials - Systems and methods for performing measurements of one or more materials are provided. One system is configured to transfer one or more materials to an imaging volume of a measurement device from one or more storage vessels. Another system is configured to image one or more materials in an imaging volume of a measurement device. An additional system is configured to substantially immobilize one or more materials in an imaging volume of a measurement device. A further system is configured to transfer one or more materials to an imaging volume of a measurement device from one or more storage vessels, to image the one or more materials in the imaging volume, to substantially immobilize the one or more materials in the imaging volume, or some combination thereof. | 01-24-2013 |
20140219528 | Methods and Systems for Image Data Processing - Methods, storage mediums, and systems for image data processing are provided. Embodiments for the methods, storage mediums, and systems include configurations to perform one or more of the following steps: background signal measurement, particle identification using classification dye emission and cluster rejection, inter-image alignment, inter-image particle correlation, fluorescence integration of reporter emission, and image plane normalization. | 08-07-2014 |