Patent application number | Description | Published |
20090161473 | METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES - A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory. | 06-25-2009 |
20100195430 | METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES - A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory. | 08-05-2010 |
20120075948 | METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES - A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory. | 03-29-2012 |
20140254273 | METHOD AND SYSTEM FOR MINIMIZING NUMBER OF PROGRAMMING PULSES USED TO PROGRAM ROWS OF NON-VOLATILE MEMORY CELLS - A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry. | 09-11-2014 |
Patent application number | Description | Published |
20120121943 | Structure and Method for Extending Battery Life - A battery sleeve for extending the operational life of one or more batteries, the battery sleeve comprising a positive conductive electrode configured such that when the battery sleeve is coupled to at least one battery, the positive conductive electrode of the sleeve serves as the new positive terminal of the at least one battery. | 05-17-2012 |
20150048785 | METHODS OF EXTENDING THE LIFE OF BATTERY - Methods for extending the life of a battery output regulated voltages from output terminals configured to interface with input terminals of battery powered devices. A method includes receiving a battery electrical power output from the battery. The voltage output by the battery decreases from a battery first output voltage to a battery second output voltage during use of the battery. The electrical power output is used to drive a converter that outputs a converter electrical power having a converter output voltage greater than the battery second output voltage. The converter electrical power is output from output terminals configured to interface with input terminals of a battery powered device. The converter is configured and supported relative to the battery to interface with one or more output terminals of the battery. | 02-19-2015 |
20150056476 | METHODS OF EXTENDING THE LIFE OF BATTERY - Methods for extending the life of a battery output regulated voltages from output terminals configured to interface with input terminals of battery powered devices. A method includes receiving a battery electrical power output from the battery. The voltage output by the battery decreases from a battery first output voltage to a battery second output voltage during use of the battery. The electrical power output is used to drive a converter that outputs a converter electrical power having a converter output voltage greater than the battery second output voltage. The converter electrical power is output from output terminals configured to interface with input terminals of a battery powered device. The converter is configured and supported relative to the battery to interface with one or more output terminals of the battery. | 02-26-2015 |
20150072181 | STRUCTURE AND METHOD FOR EXTENDING BATTERY LIFE - A battery sleeve for extending the operational life of one or more batteries, the battery sleeve comprising a positive conductive electrode configured such that when the battery sleeve is coupled to at least one battery, the positive conductive electrode of the sleeve serves as the new positive terminal of the at least one battery. | 03-12-2015 |
Patent application number | Description | Published |
20080238203 | Battery charging and power managerment circuit - Traditionally, system loads are placed in parallel with the battery. This simple topology wastes the available power if the USB power and/or wall adapter is present. Recent topologies have made some improvements by powering the load by the maximum available voltage. Thus, if a USB power source or wall adapter is present, the load is powered by them rather than the battery, thus improving the system efficiency. However, since the USB power and wall adapter power are current limited, if the load requires higher current than the current limited USB or adapter, then the entire system is powered at voltage of the battery. The present invention further improves the system efficiency by distinguishing the load and powering the constant power loads by the maximum voltage and placing the constant current loads in parallel with the battery. | 10-02-2008 |
20110018451 | Single Inductor Serial-Parallel LED Driver - An LED driver circuit is disclosed that can drive a plurality of LED strings that are arranged in parallel, each LED string having a plurality of component LEDs that are series-connected. The LED strings can be the same type of LEDs in each string, or have different types of LEDs from one string to another. The LED driver includes a voltage control loop that dynamically regulates the output voltage across the parallel arrangement of LED strings. The output voltage is dynamically adjusted to accommodate the LED string with the largest operational voltage drop. This enables LED displays to constructed using different types of LEDs strings, but still supply the LED strings in a power efficient manner. Further, each LED string also includes its own individual current regulation loop so that the current, and therefore brightness, of each LED string can be individually adjusted. | 01-27-2011 |
20120102341 | Powered Device Analysis and Power Control in a Power-Over-Ethernet System - A system and method of analyzing a powered device (PD) in a Power-over-Ethernet (PoE) system are presented. The system includes an Ethernet interface having a physical layer (PRY) chip capable of providing a signal pulse in addition to physical layer | 04-26-2012 |
Patent application number | Description | Published |
20090091994 | SYSTEM AND METHOD FOR INITIATING A BAD BLOCK DISABLE PROCESS IN A NON-VOLATILE MEMORY - A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid command, a process for disabling access to the defective portions of the array of non-volatile memory is initiated in addition to executing the initial valid command. One implementation provides receiving a memory command and determining whether an indicator has been set. In response to the indicator not being set, access to defective regions of the array of non-volatile memory is disabled in addition to executing the memory command. The indicator is also set to prevent the disabling process from being performed in response to receipt of subsequent memory commands. | 04-09-2009 |
20090257284 | METHOD AND APPARATUS FOR IMPROVING STORAGE PERFORMANCE USING A BACKGROUND ERASE - Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included is the act of asserting a background-process-busy flag after receiving the at least one erase command and the at least one erasable block address. At least one block in the memory associated with the at least one erasable block address is erased, wherein the erasing occurs at a time delay after receiving the at least one erase command if a background enable flag is asserted. Finally, the background-process-busy flag is negated after the erasing is complete. | 10-15-2009 |
20100226175 | MEMORY DEVICES AND METHODS OF WRITING DATA TO MEMORY DEVICES UTILIZING ANALOG VOLTAGE LEVELS - Memory devices, and methods of writing data to memory devices, utilizing analog voltage levels indicative of threshold voltages and desired threshold voltages of memory cells. | 09-09-2010 |
20110205800 | MEMORY DEVICES HAVING STRINGS OF SERIES-COUPLED MEMORY CELLS SELECTIVELY COUPLED TO DIFFERENT BIT LINES - Memory devices where ends of series-coupled strings of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device or by using one bit line as a ground node for sensing current flow through the strings. The use of bit lines for virtual grounding is further suitable to other array architectures. | 08-25-2011 |
20130286745 | METHOD AND APPARATUS FOR READING DATA FROM NON-VOLATILE MEMORY - Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC). | 10-31-2013 |
20140043912 | METHOD FOR KINK COMPENSATION IN A MEMORY - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 02-13-2014 |
20140098607 | SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 04-10-2014 |
20140237326 | METHOD AND APPARATUS FOR READING DATA FROM NON-VOLATILE MEMORY - Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC). | 08-21-2014 |