Patent application number | Description | Published |
20080215887 | CARD AUTHENTICATION SYSTEM - A card authentication system. In one embodiment, the invention relates to a method for authenticating a data card having an intrinsic magnetic characteristic and recorded data on the data card, the method including reading information from the data card, the data card information including the intrinsic magnetic characteristic and the recorded data on the data card, encrypting the data card information, sending the encrypted data card information, receiving the encrypted data card information, decrypting a portion of the encrypted data card information, the portion including the intrinsic magnetic characteristic, generating a score indicative of a degree of correlation between the intrinsic magnetic characteristic of the data card information and a stored value, and determining an authenticity of the data card based at least in part on the score. | 09-04-2008 |
20090060197 | Method and Apparatus for Hardware-Accelerated Encryption/Decryption - An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. A preferred embodiment of the integrated circuit includes a symmetric block cipher that may be scaled to strike a favorable balance among processing throughput and power consumption. The modular architecture also supports multiple encryption modes and key management functions such as one-way cryptographic hash and random number generator functions that leverage the scalable symmetric block cipher. The integrated circuit may also include a key management processor that can be programmed to support a wide variety of asymmetric key cryptography functions for secure key exchange with remote key storage devices and enterprise key management servers. Internal data and key buffers enable the device to re-key encrypted data without exposing data. The key management functions allow the device to function as a cryptographic domain bridge in a federated security architecture. | 03-05-2009 |
20090182683 | Method and System for Low Latency Basket Calculation - A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA). | 07-16-2009 |
20090287628 | Method and System for Accelerated Stream Processing - Disclosed herein is a method and system for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams. | 11-19-2009 |
20100094858 | Method and System for High Performance Integration, Processing and Searching of Structured and Unstructured Data Using Coprocessors - Disclosed herein is a method and system for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. Queries can be directed toward both an enterprise's structured and unstructured data using standardized database query formats such as SQL commands. A coprocessor can be used to hardware-accelerate data processing tasks (such as full-text searching) on unstructured data as necessary to handle a query. Furthermore, traditional relational database techniques can be used to access structured data stored by a relational database to determine which portions of the enterprise's unstructured data should be delivered to the coprocessor for hardware-accelerated data processing. | 04-15-2010 |
20120095919 | SYSTEMS AND METHODS FOR AUTHENTICATING ASPECTS OF AN ONLINE TRANSACTION USING A SECURE PERIPHERAL DEVICE HAVING A MESSAGE DISPLAY AND/OR USER INPUT - Systems and methods for authenticating aspects of an online transaction using a secure peripheral device having a message display and/or user input are provided. One such method for establishing a secure communication channel between a computer peripheral device and a host includes responding to requests to authenticate the peripheral device, authenticating the host, receiving one or more messages from the host, displaying the one or more messages on a display of the peripheral device, receiving user input in response to the one or more messages, sending the user response to the host. | 04-19-2012 |
20120109849 | Intelligent Data Storage and Processing Using FPGA Devices - A re-configurable logic device such as a field programmable gate array (FPGA) can be used to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data processing engines, the plurality of pipelined data processing engines including a data reduction engine, the plurality of pipelined data processing engines being configured to perform processing operations, wherein the pipeline comprises a multi-functional pipeline, and wherein the re-configurable logic device is further configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. | 05-03-2012 |
20120110316 | Intelligent Data Storage and Processing Using FPGA Devices - A re-configurable logic device such as a field programmable gate array (FPGA) can be used to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations, wherein the pipeline comprises a multi-functional pipeline, and wherein the re-configurable logic device is further configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. | 05-03-2012 |
20120116998 | Method and Apparatus for Processing Financial Information at Hardware Speeds Using FPGA Devices - A method and apparatus use a reconfigurable logic device to process a stream of financial information at hardware speeds. The reconfigurable logic device can be configured to perform data processing operations on the financial information stream. Examples of such data processing operations include data processing operations to compute a latest stock price, a minimum stock price, and a maximum stock price. | 05-10-2012 |
20120130922 | Method and Apparatus for Processing Financial Information at Hardware Speeds Using FPGA Devices - A method and apparatus use hardware logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The hardware logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operations include data processing operations to compute a latest stock price, a minimum stock price, and a maximum stock price. | 05-24-2012 |
20120215801 | Method and Apparatus for Adjustable Data Matching - A method and apparatus for performing a matching operation on data are disclosed. With an exemplary embodiment, a programmable logic device can be used to search for data of interest to an application, where the programmable logic device processes streaming data against a data key to generate a signal indicative of a similarity between the streaming data and the data key and compares the generated signal with a defined threshold to thereby determine whether the streaming data is deemed a match to the data key, wherein the threshold is adjustable to control whether the programmable logic device performs an approximate match operation or an exact match operation, and further to control, for an approximate match operation, a degree of approximate matches returned by the approximate match operation. | 08-23-2012 |
20130007000 | Method and System for High Performance Integration, Processing and Searching of Structured and Unstructured Data Using Coprocessors - Disclosed herein is a method and system for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of metadata indexes about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device to generate the metadata about the unstructured data for the index. | 01-03-2013 |
20130086096 | Method and System for High Performance Pattern Indexing - Disclosed herein is a method and system for accelerating the generation of pattern indexes. In exemplary embodiments, regular expression pattern matching can be performed at high speeds on data to determine whether a pattern is present in the data. Pattern indexes can then be built based on the results of such regular expression pattern matching. Reconfigurable logic such a field programmable gate arrays (FPGAs) can be used to hardware accelerate these operations. | 04-04-2013 |
20130148802 | Method and System for High Throughput Blockwise Independent Encryption/Decryption - An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A corresponding decryption technique is also disclosed. | 06-13-2013 |
20130151458 | Method and Apparatus for Accelerated Data Quality Checking - Disclosed herein is a method and apparatus for hardware-accelerating various data quality checking operations. Incoming data streams can be processed with respect to a plurality of data quality check operations using offload engines (e.g., reconfigurable logic such as field programmable gate arrays (FPGAs)). Accelerated data quality checking can be highly advantageous for use in connection with Extract, Transfer, and Load (ETL) systems. | 06-13-2013 |
20130262287 | Offload Processing of Data Packets Containing Financial Market Data - Various techniques are disclosed for offloading the processing of data packets that contain financial market data. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize financial market data in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform. | 10-03-2013 |
20140025656 | Method and Apparatus for Processing Streaming Data Using Programmable Logic - Methods and apparatuses for processing streaming data using programmable logic are disclosed. With an exemplary embodiment, a programmable logic device can be used to sort streaming data and provide a processor with access to the sorted data. With another exemplary embodiment, an Internet search engine can include a programmable logic device to perform match operations in response to search queries for web pages. With another exemplary embodiment, a programmable logic device is configured to perform match operations on streaming data while a processor is freed to perform other tasks. | 01-23-2014 |
20140180903 | Offload Processing of Data Packets - Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform. | 06-26-2014 |
20140180904 | Offload Processing of Data Packets Containing Financial Market Data - Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform. | 06-26-2014 |
20140180905 | Intelligent Switch for Processing Financial Market Data - Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform. | 06-26-2014 |
20140181133 | Intelligent Feed Switch - Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data from the data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform. | 06-26-2014 |
20140310717 | Intelligent Data Storage and Processing Using FPGA Devices - A re-configurable logic device such as a field programmable gate array (FPGA) can be used to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations, wherein the pipeline comprises a multi-functional pipeline, and wherein the re-configurable logic device is further configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. | 10-16-2014 |
20150023501 | Method and Apparatus for Hardware-Accelerated Encryption/Decryption - An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. An embodiment of the integrated circuit includes a run-time scalable block cipher circuit, wherein the run-time scalable block cipher circuit is run-time scalable to balance throughput with power consumption. | 01-22-2015 |
20150052148 | Method and System for High Performance Integration, Processing and Searching of Structured and Unstructured Data Using Coprocessors - Disclosed herein is a method and system for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. In accordance with exemplary embodiments, the generation of metadata indexes about unstructured data can be hardware-accelerated by processing streaming unstructured data through a reconfigurable logic device to generate the metadata about the unstructured data for the index. | 02-19-2015 |
20150055776 | Method and System for High Throughput Blockwise Independent Encryption/Decryption - An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A corresponding decryption technique is also disclosed. | 02-26-2015 |