Patent application number | Description | Published |
20080215805 | DIGITAL DATA BUFFER - A data buffer with a mechanism to optimize the setup/hold timing at the second flip-flop (or data register) so as to reduce the propagation delay time. The data buffer has a data path with a data input for receiving a digital data input signal, a clock input for receiving a clock input signal and a data output providing a digital data output signal for application to a data destination device, e.g. a RAM module in a memory system. The data buffer further has a clock output for providing an output clock signal to the data destination device and a phase locked loop (PLL) with a phase aligner and a first and second data register with respective clock inputs. The data input of the first data register is selectively coupled to the data input of the buffer or to a reference data input through a multiplexer. A reference data path is provided in parallel with the data path including a third data register with a data input to which the reference data input is coupled and a reference data output. A second clock output of the phase locked loop provides a clock signal shifted in phase by the phase aligner with respect to a feedback clock signal for application to the clock input of the second data register and to the clock input of the third data register. The data output of the second data register and the reference data output of the third data register are applied to inputs of a logic circuit that has a control output. The phase aligner in the phase locked loop has associated control circuitry with a control input coupled to the control output of the logic circuit. A learn cycle control signal is applied in parallel to the multiplexer and to the control circuitry of the phase aligner causing the phase aligner in a learn cycle to adjust the phase of the clock signal at the second clock output of the phase locked loop so as to optimise the setup/hold timing at the data input of the second data register. | 09-04-2008 |
20080301485 | REGISTER WITH PROCESS, SUPPLY VOLTAGE AND TEMPERATURE VARIATION INDEPENDENT PROPAGATION DELAY PATH - The digital data register has a plurality of parallel matched data paths, each data path having a data input for receiving a digital data input signal (CA/CNTRL), an output driver with a data output providing a digital data output signal (Q_CA/CNTRL) for application to an associated memory module and a flip-flop (FF1) arranged between the data input and the data output. The data register further comprises a clock input for receiving a clock input signal (CLK), a clock output for providing an output clock signal (Q_CLKn, Q_NCLKn) to the memory modules, a phase locked loop (PLL) with a clock input (REF), a feedback input (FB), a feedback output providing a feedback output signal (Q_NFB) and a clock output providing a clock output signal (Q_CLK, QNCLK). In addition a flip-flop (FF1 DELAY) and output driver replica are matched with the flip-flop and output driver of the data paths. the flip-flops (FF1) of the data paths and the flip-flop (FF1 DELAY) of the replica are clocked by the feedback signal applied to the feedback input (FB) of the phase locked loop (PLL). The phase locked loop (PLL) includes a phase aligner with a phase interpolator. The phase interpolator has an output that provides the output clock signal (Q_CLKn, Q_NCLKn) to the memory modules through a flip-flop (FF1 DELAY) and output driver matched with the flip-flop and output driver of the data paths. A phase frequency detector (PFD) has a first input (REF) coupled to the output of the output driver replica and a second input (SYS) coupled to the clock output. The phase interpolator is controlled by the output of the phase frequency detector (PFD). The proposed data register satisfies the three requirements of: (i) setup and hold timing on the pre-register side, (ii) clock centering on the post-register side, and (iii) constant propagation delay time (tpd) over PVT variations from the clock input to the data output. | 12-04-2008 |
20080313485 | DATA PIPELINE WITH LARGE TUNING RANGE OF CLOCK SIGNALS - The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time. | 12-18-2008 |
Patent application number | Description | Published |
20080206603 | Arrangement Having a Battery | 08-28-2008 |
20080219441 | Arrangement Comprising an Integrated Circuit - An integrated circuit ( | 09-11-2008 |
20100100749 | Single-Chip Computer and Tachograph - A single-chip computer includes at least one first processor core and at least one second processor core constructed on a common chip. The at least one first and the at least one second processor cores are interconnected via a processor interface. Data can be read via a separate or common memory interface from a separate or common data memory respectively and/or stored in said data memory. The single-chip computer includes an encryption and decryption unit which is assigned to the at least one processor core and which is constructed and functionally arranged between the at least one second processor core and the memory interface in such a way that the data which can be exchanged between the at least one second processor core and the data memory can be encrypted and decrypted by the encryption and decryption unit. | 04-22-2010 |
20100209747 | Energy Storage Unit - An energy storage unit, particularly for a motor vehicle, has an application unit that is configured to detect and/or process predetermined operating parameters of the energy storage unit. The energy storage unit further includes a safety unit that is configured to cryptologically process the detected and/or processed operating parameters. The energy storage unit also includes a communication interface for making the cryptologically processed operating parameters available. | 08-19-2010 |
20100250053 | Tachograph, Toll Onboard Unit, Display Instrument, and System - A tachograph and a toll onboard unit as communication partners, which each have a data interface for a data communication via a vehicle data bus to which the communication partners are coupled. The tachograph and/or the toll onboard unit are implemented as a transmitter of data to ascertain a cryptographic check value as a function of user data, which are to be transmitted to the communication partner, and to transmit the cryptographic check value in addition to the user data to the communication partner. The toll onboard unit or the tachograph, respectively, as a receiver of data, is implemented to receive user data and the cryptographic check value associated with the user data from the communication partner and to check the received user data for corruption as a function of the received cryptographic check value. | 09-30-2010 |
20100284235 | Method and Control Unit for Operating a Volatile Memory, Circuit Arrangement, and Trip Recorder - A method for operating a volatile memory supplied with a supply signal arranged either as a first supply signal of a first supply signal source or a second supply signal of a second supply signal source. If an available first supply signal is present it is used otherwise the second supply signal is used. The supply signal is supplied, based on a switch position of a switching element to the volatile memory. During a detected interrupted first supply signal, the switch position of the switching element is for a predetermined period of time such that the supply signal is supplied to the volatile memory. After expiry of the predetermined period of time, the switch position of the switching element is predetermined such that the volatile memory is decoupled electrically from the supply signal. | 11-11-2010 |
20110137490 | MOBILE INTERFACE AND SYSTEM FOR CONTROLLING VEHICLE FUNCTIONS - A mobile interface for controlling a plurality of vehicle functions in a motor vehicle using a controller connected to the vehicle, having a wireless data interchange with a controller, an input apparatus, and an energy store. By virtue of the wireless data interchange being connected to a data processing unit integrated in the mobile interface and which is designed to apply at least one cryptological method, a greater scope of functions becomes possible that can also include control of safety-relevant vehicle functions. | 06-09-2011 |
20120245757 | Vehicle Data Recording Device - A vehicle data recording device including a vehicle data recording unit which has a housing, a data memory arranged outside the housing, and a unit interface with a connection for the data memory is provided in an outer wall of the housing. The data memory is connected to the unit interface by a connecting cable. To ensure not only that the data memory is reliably arranged in the vehicle data recording device but also that the data memory can be easily removed from the device, the housing has, on a housing outer side, a mount that detachably supports the data memory. | 09-27-2012 |
20120303177 | DOCKING TERMINAL AND SYSTEM FOR CONTROLLING VEHICLE FUNCTIONS - A docking terminal for controlling a plurality of vehicle functions of a motor vehicle by a control device connected to the vehicle, including a wireless data exchange with a control device, an input unit, and an energy store. A greater range of functions, which can also include control of safety-relevant vehicle functions, is facilitated by the connection of the wireless data exchange to a data processing system integrated in the docking terminal. The system is designed to use at least one cryptologic method. | 11-29-2012 |
Patent application number | Description | Published |
20090304041 | Apparatus for the Determination of the Surface Moisture of a Test Object - An apparatus for determining the moisture of a surface, particularly a wall surface device for determining a room dew point, a surface temperature device for determining the surface temperature by means of an infrared radiation measuring instrument, and an assembly for determining the surface moisture from the room dew point and the surface temperature. | 12-10-2009 |
20090314053 | Device for calibration of a humidity sensor and a sensor arrangement with a humidity sensor which may be calibrated - A device for calibration of a humidity sensor with a measuring chamber includes a first gas connector for connection to a pressurizing unit and a second gas connection for connection to a further gas chamber. The first and/or the second gas connector may have a flow resistance which may be adjusted to two different fixed values. | 12-24-2009 |
20100043567 | MEASURING ARRANGEMENT FOR FLOW MEASUREMENT IN A CHANNEL - A measuring arrangement for determining flow speeds in a flow channel includes a probe tube which is introduced via a first opening into the flow channel. The probe tube is exposed to a flow with a flow speed, the side of the probe tube facing the flow comprising a plurality of openings which are interconnected inside the probe tube such that a total pressure dependent on the flow speed prevails inside the probe tube. The measuring arrangement also comprises a static pressure opening in the flow channel, and a differential pressure sensor that determines the differential pressure between the total pressure inside the probe and the static pressure in the flow channel. The probe tube may be partially surrounded by a shield which is mobile and/or length-adjustable and that, according to its position and/or length along the probe tube, may close one, several or none of the openings. | 02-25-2010 |
20150030053 | TEMPERATURE MEASURING DEVICE, TEMPERATURE MEASURING DEVICE SET AND METHOD FOR CONFIGURING A TEMPERATURE MEASURING DEVICE THAT CAN BE OPERATED WITH A THERMOCOUPLE - In a temperature measuring device set ( | 01-29-2015 |
20150198468 | VOLUMETRIC-FLOW MEASURING APPARATUS - A volumetric-flow measuring apparatus ( | 07-16-2015 |
Patent application number | Description | Published |
20100043554 | APPARATUS FOR ASCERTAINING AND/OR MONITORING A PROCESS VARIABLE OF A MEDIUM - An apparatus including: a mechanically oscillatable unit; an exciting/receiving unit; and an electronics unit having an input amplifier and an output amplifier. The amplification factors of the output amplifier and the input amplifier are tunable. The control unit tunes the amplification factor of the output amplifier as a function of damping of the mechanically oscillatable unit in such a manner that the amplitude of the electrical, input signal lies within an amplitude band and that the amplification factor of the output amplifier decreases in the case of lessened damping by the medium and increases in the case of greater damping by the medium, and the control unit tunes the amplification factor of the output amplifier and the amplification factor of the input amplifier in such a manner that the total amplification factor of the electronics unit equals a predeterminable value. | 02-25-2010 |
20100161251 | METHOD FOR DETERMINING AND/OR MONITORING A PROCESS VARIABLE OF A MEDIUM, AND CORRESPONDING APPARATUS - Method for determining and/or monitoring a process variable of a medium, wherein a mechanically oscillatable unit is supplied with an exciter signal wherein a received signal coming from the mechanically oscillatable unit is received, and wherein the exciter signal is produced in such a manner, that a phase difference between the exciter signal and the received signal equals a predeterminable phase value. A criterion for judging the determining of the phase difference between the exciter signal and the received signal, or a signal dependent on the exciter signal or on the received signal, is established; in the case, in which the criterion for judging the determining of the phase difference is fulfilled, tuning of the phase difference is closed-loop controlled; and, in the alternative case, tuning of the phase difference is open-loop controlled. An apparatus associated with the method is also disclosed. | 06-24-2010 |