Patent application number | Description | Published |
20080246110 | STRUCTURE FOR SPANNING GAP IN BODY-BIAS VOLTAGE ROUTING STRUCTURE - Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire. | 10-09-2008 |
20080303600 | Dynamic Ring Oscillators - A dynamic oscillating ring circuit is described, which has multiple non-inverting domino circuits, each having a signal input, a trigger input, inputs for charge state clock and clocked cutoff and an output inverter. A number of the domino circuits are coupled in series, the output of one feeding the input of the next, to form a chain, which form stages of the ring. A number of the stages are coupled in series, the output of one feeding the input of the next, to form the ring. The first domino circuit of said chain receives a logic signal input and a single trigger input for the chain. Within the ring, the output of each stage feeds the input signal to the next stage and is fed back to clock an earlier stage to allow the ring to oscillate. | 12-11-2008 |
20090212815 | TRIPLE LATCH FLIP FLOP SYSTEM AND METHOD - A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch. | 08-27-2009 |
20100127749 | PRECISION PULSE GENERATOR - A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node. | 05-27-2010 |
20100148843 | BOW TIE CLOCK DISTRIBUTION - A clock distribution network includes: a primary clock signal and a distribution tree coupled to the primary clock signal. The distribution tree derives a plurality of separate clock signals from the primary clock signal and provides each of the plurality of separate clock signals to each of a plurality of loads. The distribution tree comprises a plurality of bow tie elements. | 06-17-2010 |
20100156504 | CROSS POINT SWITCH - A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches. | 06-24-2010 |
20100164447 | STATIC-DYNAMIC-DYNAMIC REPEATER CIRCUIT - A repeater circuit. The repeater circuit includes two input circuits, two intermediate circuits, and two output circuits. Responsive to a transition of an input signal from one logic level to another level, one of the input circuits is activated. The corresponding intermediate circuit is activated corresponding to activation one of the input circuits, and in turn, the corresponding output circuit is activated, which then drives an output signal on an output node. After a delay, a feedback signal conveyed via a feedback path deactivates the corresponding intermediate circuit and the corresponding output circuit. After deactivation of the corresponding output circuit, a keeper circuit continues to provide the output signal on the output node. The other one of the two input circuits inhibits activation of the other one of the intermediate circuit responsive to the transition, which results in the other output circuit also being inhibited from activation. | 07-01-2010 |
20100164556 | CONVERTING DYNAMIC REPEATERS TO CONVENTIONAL REPEATERS - A method for converting a repeater circuit from a dynamic repeater circuit to a static repeater circuit. The method includes disconnecting a feedback path coupled to a first stage of the dynamic repeater circuit and electrically shorting gate terminals of first and second transistors of a second stage to each other, wherein the transistors of the second stage are configured to drive an output signal on an output node. Disconnecting the feedback path and electrically shorting the gate terminals is performed by reconfiguring a plurality of selection devices in the repeater circuit from a first configuration to a second configuration. The repeater circuit includes at least one keeper configured to provide an output signal on the output node. | 07-01-2010 |
20100164557 | ACTIVE ECHO ON-DIE REPEATER CIRCUIT - A repeater circuit. The repeater circuit includes two output circuits, two echo circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, which is configured to drive an output signal on an output node. A corresponding echo circuit is configured to be activated and to drive an input node responsive to activation of the corresponding output circuit. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the corresponding echo circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuit. | 07-01-2010 |
20100164576 | TRANSIT STATE ELEMENT - A transit state element circuit. The transit state element circuit includes a clock input stage coupled to receive a clock signal, an output stage configured to drive an output signal on an output node and an activation stage coupled to an input node. The activation stage is configured to, responsive to the clock input stage detecting a transition from a first logic level to a second logic level and detecting a logical transition of an input signal on the input node, activate the output stage to drive an output signal on the output node. A storage element is configured to capture a logic value of the input signal when the clock is at the second logic level and to store the logic value, and to provide the output signal on the output node when the clock signal is at the first logic level. | 07-01-2010 |
20100164578 | REPEATER CIRCUIT WITH STAGED OUTPUT - A repeater circuit. The repeater circuit includes a first output stage having two output circuits, a second output stage having two additional output circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, and responsive thereto another corresponding output circuit is configured to be activated. The output circuits drive an output signal on the output node. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the other corresponding output circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuits. | 07-01-2010 |
20100181685 | INTEGRATED CLOCK AND POWER DISTRIBUTION - An integrated clock and power distribution network in a semiconductor device includes assigning a first tile to a location on a placement grid corresponding to a top metal layer. An orientation is assigned to the first tile relative to the top metal layer placement grid. The first tile is placed on a representation corresponding to the top metal layer in accordance with the assignments. A second tile is assigned to a location on a placement grid corresponding to a top-1 metal layer. The orientation is assigned to the second tile relative to the top-1 metal layer placement grid. The second tile is placed on a representation corresponding to the top-1 metal layer in accordance with the assignments. The first and second tile are arranged as a full-dense-mesh distribution structure. The first tile includes an integrated clock and power distribution structure. The second tile includes a low impedance underpass structure. | 07-22-2010 |
20100188130 | LOW RC LOCAL CLOCK DISTRIBUTION - A system includes an input device, an output device, a printed circuit board, and a semiconductor device. The semiconductor device includes a semiconductor die. The semiconductor die includes a clock distribution network that distributes a primary clock signal. The clock distribution network includes a low RC local clock distribution structure. The low RC local clock distribution structure includes a conductor, a first clock signal incident on the conductor, a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal, and a shorting bar that shorts the second clock signal to a plurality of conductors. | 07-29-2010 |
20100229142 | LOW RC GLOBAL CLOCK DISTRIBUTION - A semiconductor die includes: a clock distribution network that distributes a clock signal within the die. The clock distribution network includes: a clock tree corresponding to one or more metal layers of the die, a plurality of clock spines corresponding to a metal layer of the die, a plurality of clock wings corresponding to a metal layer of the die, a plurality of clock grid drivers placed in one or more gaps of a floorplan corresponding to the semiconductor layer of the die, a clock grid placed in the one or more gaps of the floorplan, a plurality of buffers placed in a local gain buffer pair configuration wherein the local gain buffer pair connects the clock grid to a shorting bar, and a plurality of conductors that connect the shorting bar to a plurality of loads. | 09-09-2010 |
20100235716 | DUAL PORTED REPLICATED DATA CACHE - A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block. | 09-16-2010 |
20100264973 | ECONOMY PRECISION PULSE GENERATOR - A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse. The output pulse is fed back to the pull-down-against-the-up-keeper circuit. | 10-21-2010 |
20100271076 | PRECISION SAMPLING CIRCUIT - A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input. | 10-28-2010 |
20100271085 | DELAY CHAIN INITIALIZATION - A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous. | 10-28-2010 |
20100271099 | FINE GRAIN TIMING - A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain. | 10-28-2010 |
20100271100 | MINIMAL BUBBLE VOLTAGE REGULATOR - A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator. | 10-28-2010 |
20100301914 | LATCH WITH CLOCKED DEVICES - A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device, and a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device, and a keeper circuit. The first output is operatively connected to the second input. The keeper circuit is operatively connected to the first output, and the keeper circuit is driven from the second output. The feed-back circuit includes a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output, and a fourth-inverting-stage with a fourth input and a fourth output. The fourth input is operatively connected to the third output. The fourth output is connected to the third input to form a storage node. | 12-02-2010 |
20100301915 | LATCH WITH SINGLE CLOCKED DEVICE - A D-latch circuit includes a feed forward circuit, a full keeper circuit, and an output buffer circuit. The feed forward circuit inputs a clock signal and a data signal. The feed forward circuit is connected to an input of the full keeper circuit. The feed forward circuit is connected to an output of the full keeper circuit and an input of the output buffer circuit. The output buffer circuit outputs an output signal. The D-latch consists of a single clocked device that switches with the clock signal. | 12-02-2010 |
20100316065 | METHOD AND APPARATUS FOR MODULATING THE WIDTH OF A HIGH-SPEED LINK - The described embodiments include a system that modulates the width of a high-speed link. The system includes a transmitter circuit coupled to a high-speed link that includes N serial lanes. During operation, while using a first number of lanes to transmit frames on the high-speed link, the transmitter circuit determines a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link. The transmitter circuit then sends an indicator of the second number of lanes to a receiver on the high-speed link. Upon receiving an error-free acknowledgment of the indicator from the receiver, starting from a predetermined frame, the transmitter circuit transmits subsequent frames on the high-speed link using the second number of lanes. | 12-16-2010 |
20100327937 | CONFIGURABLE PULSE GENERATOR - The described embodiments provide a circuit that can be configured as a pulse generator or as an oscillator. The circuit includes a pulse generator circuit and a test circuit that is coupled to the pulse generator circuit. In the described embodiments, an disable signal is coupled to the test circuit. When the disable signal is asserted, the test circuit is disabled, and the pulse generator circuit outputs pulses of a predetermined duration. In contrast, when the disable signal is deasserted, the test circuit is enabled, and the pulse generator circuit outputs an oscillating signal. | 12-30-2010 |
20100327982 | INVERTING DIFFERENCE OSCILLATOR - The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO. | 12-30-2010 |
20110072326 | SRAM MACRO TEST FLOP - A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit. | 03-24-2011 |
20110121906 | INVERTING DIFFERENCE OSCILLATOR - The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO. | 05-26-2011 |
20110147915 | COMBINED POWER MESH TRANSITION AND SIGNAL OVERPASS/UNDERPASS - A zipper structure includes a first contiguous full-dense-mesh (FDM) array of a first supply in top metal and a second contiguous FDM array of a second supply in top-1 metal, a third contiguous FDM array of the second supply in top metal and a fourth contiguous FDM array of the first supply in top-1 metal, and a signal line, such that portions of the first contiguous FDM array and the second contiguous FDM array overlap and portions of the third contiguous FDM array and the fourth contiguous FDM array overlap. The Zipper structure facilitates connecting the first contiguous FDM array to the fourth contiguous FDM array by VIAs and a first connector lines and the second contiguous FDM array to the third contiguous FDM array by VIAs and a second connector lines, such that portion of the signal line overlaps with the first connector lines and the second connector lines. | 06-23-2011 |
20110254669 | FAST REPEATER LATCH - A repeater circuit is disclosed. The repeater circuit includes an input circuit coupled to receive a data input signal and a clock signal, and an output circuit configured to, when activated, drive an output signal on an output node. The input circuit is further configured to activate the output circuit in order to initiate a logical transition of the data output signal. A deactivation circuit is configured to deactivate the output circuit at a delay subsequent to activation. A latch is coupled the output circuit and it is configured to change a latch output state responsive to activation of the output circuit. The latch is configured to hold a state the output node subsequent to deactivation of the output circuit. The input circuit is configured to activate the output circuit dependent on the clock signal. The deactivation circuit is configured to deactivate the output circuit independent of the clock signal. | 10-20-2011 |
20120081157 | POWER-SUPPLY NOISE SUPPRESSION USING A FREQUENCY-LOCKED LOOP - An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic. | 04-05-2012 |
20120099622 | REPEATER CIRCUIT WITH MULTIPLEXER AND STATE ELEMENT FUNCTIONALITY - A circuit implementing multiplexer, storage, and repeater functions is disclosed. The circuit includes first and second input stages having first and second data inputs, respectively. An output stage is configured to drive an output signal. The first input stage is configured to activate the output stage responsive to a first condition, while the second input stage is configured to activate the output stage responsive to a second condition. An intermediate stage is configured to deactivate the output stage at a first delay time subsequent to one of the first or second input stages activating the output stage. The repeater circuit also includes a storage element configured to store a state of the output signal, and further configured to cause the output node to be held at the state of the output signal subsequent to deactivation of the output stage. | 04-26-2012 |
20120161839 | INVERTING ZIPPER REPEATER CIRCUIT - Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described. | 06-28-2012 |
20120169392 | MIN-TIME HARDENDED PULSE FLOP - A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit. | 07-05-2012 |
20120182055 | FLOP TYPE SELECTION FOR VERY LARGE SCALE INTEGRATED CIRCUITS - A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC. | 07-19-2012 |
20120200347 | SKEWED PLACEMENT GRID FOR VERY LARGE SCALE INTEGRATED CIRCUITS - A skewed placement grid for an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a placement grid which includes a plurality of cells. Each of the plurality of cells includes one of a corresponding plurality of circuits. A center point of each of the cells is located at a unique coordinate along a first axis and a second axis with respect to each of the other ones of the plurality of cells. The IC further includes a first plurality of signal interconnections, wherein each of the plurality of signal interconnections is coupled to a corresponding one of the first plurality of circuits. | 08-09-2012 |
20120210040 | MICRO-CROSSBAR AND ON-DIE DATA NETWORK - An integrated circuit (IC) having an on-die data network is disclosed. The IC includes a first bus and second buses configured to convey signals in first and second directions, respectively, along a first axis. The second direction is opposite the first. The IC further includes third and fourth buses configured to convey signals in third and fourth directions, respectively, along a second axis perpendicular to the first axis. The fourth direction is opposite the third. Each bus is N-bits wide and unidirectional. Signal lines of two different buses having equal bit significance and opposite direction are arranged adjacent to one another. A crossbar unit having N crossbar switching circuits is configured to couple signal lines of a selected one of the buses to a corresponding signal line of another selected one of the buses. The signal lines of the buses are implemented on different metal layers than the crossbar switching circuits. | 08-16-2012 |
20120212269 | SINGLE-INVERSION PULSE FLOP - A single inversion pulse flop includes a critical evaluation path with a single inverter and a storage feedback loop arranged in parallel with the critical evaluation path. The single inversion pulse flop incurs a single inversion delay and does not require an output buffer. | 08-23-2012 |
20120224448 | DELAY EFFICIENT GATER REPEATER - A gater repeater circuit is disclosed. In one embodiment, the circuit includes an activation circuit coupled to receive an input signal and a clock signal and configured to activate an output circuit. The output circuit is configured to drive an output signal. The output circuit includes first and second devices configured to drive the output signal to first and second states, respectively. A feedback circuit is configured to provide a delayed version of the output signal. A deactivation circuit is coupled to receive the clock signal and the delayed version of the output signal, and is configured to, when the clock signal is in the first state, cause the deactivation of an active one of the first and second devices. When the clock is in the second state, the circuit is configured to cause the second device to drive the output signal to the second state. | 09-06-2012 |
20120326327 | VIA STRUCTURE FOR INTEGRATED CIRCUITS - An integrated circuit (IC) having a concentric arrangement of stacked vias is disclosed. The IC includes first and second pluralities of signal lines on first and second metal layers, respectively. The second metal layer is arranged between the first metal layer and a silicon layer. The IC also includes a via structure implemented in a predefined area, and connects each of the first and second pluralities of signal lines to circuitry in the silicon layer through respective first and second pluralities of vias. Each via of the first and second pluralities has a center point that extends along a vertical axis from its respective metal layer to the silicon layer. Centers of each of the second plurality of vias are closer to a perimeter of the predefined area than respective centers of any of the first plurality of vias. | 12-27-2012 |
20130043921 | GLITCH HARDENED FLOP REPEATER - A repeater circuit is disclosed. The circuit includes an input stage configured to receive an input signal and a clock signal. An output stage is configured to drive an output signal on an output node to a first state responsive to a first transition of the input signal on the input node concurrent with a first phase of the clock signal. The input stage is configured to activate a first driver circuit of the output stage responsive to a first transition of the input signal. A reverse stage is configured to assert a first inhibit signal at a delay time subsequent to activation of the first driver circuit, which is configured to be deactivated responsive to assertion of the first inhibit signal. Assertion of the first inhibit signal is prevented responsive to a second transition of the input data signal occurring before the delay time has elapsed. | 02-21-2013 |
20130254448 | MICRO-LINK HIGH-BANDWIDTH CHIP-TO-CHIP BUS - A chip package includes a micro-link between components disposed on a substrate. The micro-link may be an ultra-short multi-conductor transmission line with shared reference planes that results in a distribution of impedance values. Furthermore, the composite signal traces in the transmission line each can support communication of one symbol at a time by ensuring that multiple reflections reach a substantial fraction of a steady-state value within a symbol time. In this way, the micro-link may facilitate continued scaling of the communication bandwidth between the components with low latency to increase the performance of computer systems that include the chip package. | 09-26-2013 |
20140047284 | COMBO STATIC FLOP WITH FULL TEST - A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit. | 02-13-2014 |
20140131833 | BODY-BIAS VOLTAGE ROUTING STRUCTURES - Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit. | 05-15-2014 |
20140136912 | COMBO DYNAMIC FLOP WITH SCAN - A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit. | 05-15-2014 |
20140140147 | STATIC RANDOM ACCESS MEMORY CIRCUIT WITH STEP REGULATOR - Implementations of the present disclosure involve a circuit and/or method for providing a static random access memory (SRAM) component of a very large scale integration (VLSI) design, such as a microprocessor design. In particular, the present disclosure provides for an SRAM circuit that includes a step voltage regulator coupled to the SRAM circuit and designed to maintain a fixed-value voltage drop across the regulator rather than a fixed voltage across the load of the SRAM circuit. The fixed-value drop across the regulator allows the SRAM circuit to be operated at a low retention voltage to reduce leakage of the SRAM circuit while maintaining the parasitic decoupling capacitance across the power supply from the SRAM circuit to reduce power signal fluctuations. In addition, the regulator circuit coupled to the SRAM circuit may include a switch circuit to control the various states of the SRAM circuit. | 05-22-2014 |
20140140205 | POST-SILICON REPAIR OF ON-DIE NETWORKS - A method and apparatus for post-silicon repair of on-die networks is disclosed. In one embodiment, an integrated circuit includes a first network node of an on-chip network configured to couple each of a plurality of functional units to at least one other one of the plurality of functional units. The first network node includes a plurality of ports. Each of the plurality of ports includes a plurality of multiplexers configured to substitute a spare channel of the network node into the network responsive to a test determining that another one of a plurality of channels is defective. | 05-22-2014 |
20140169117 | DECODER CIRCUIT WITH REDUCED CURRENT LEAKAGE - A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic. | 06-19-2014 |
20140210516 | Level Shifter Circuit Optimized for Metastability Resolution and Integrated Level Shifter and Metastability Resolution Circuit - A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal. | 07-31-2014 |
20140210526 | Rotational Synchronizer Circuit for Metastablity Resolution - A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input. | 07-31-2014 |