Rino
Rino Choi, Seoul KR
Patent application number | Description | Published |
---|---|---|
20090294867 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 12-03-2009 |
20120256270 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 10-11-2012 |
Rino D'Aloisio, Novara IT
Patent application number | Description | Published |
---|---|---|
20100210483 | PROCESS FOR THE REMOVAL OF FILTERCAKES IN OIL WELLS - Process for the solubilization of polymeric material deposited on a porous medium, which comprises putting said polymeric material in contact with an aqueous composition comprising: (a) a catalyst selected from: (a1) a complex having general formula (I), Fe | 08-19-2010 |
Rino D'Amario, Sigirino CH
Patent application number | Description | Published |
---|---|---|
20120243620 | METHOD AND APPARATUS FOR DIGITAL DATA TRANSMISSION - An expansion of known serial data links, for example ETHERNET, published in IEEE802.3, for directly transmitting random events without having to carry out synchronization with a clock signal or having to wait for a cyclical transmission time. Two different, random events are represented using two differently coded individual pulses and are transmitted in an event-controlled manner. A jitter-free latency of 45 ns between the event and its reception is possible over a line length of 8 m, for example. The expansion is particularly suitable for the short, digital data links between a node and a plurality of modules, as are required in modern electrical discharge machines, machine tools and similar electronic systems. | 09-27-2012 |
20150060412 | ELECTRIC DISCHARGE MACHINE - The invention relates to a pulse generator module ( | 03-05-2015 |
Rino Durio, Piobesi D'Alba (cuneo) IT
Patent application number | Description | Published |
---|---|---|
20120244250 | PROCESS AND APPARATUS FOR PRODUCING BAKERY PRODUCTS IN THE FORM OF HALF-SHELLS - In a process for producing half-shells ( | 09-27-2012 |
Rino Marazzi, Pratteln CH
Patent application number | Description | Published |
---|---|---|
20090025151 | Light-Fast Dyeings on Bicomponent Fibers - Process for improving the light-fastness of dyeings on multicomponent fibres composed of a thermodynamically compatible polyolefin and polyamide with disperse dyes characterized in that they are subjected to a treatment with benzotriazole derivatives. | 01-29-2009 |
20090100611 | Acid Dye Composition of Anthraquinone Dyes - An acid dye composition comprising a dyestuff according to the formula (I) | 04-23-2009 |
20090158534 | Dyeing of Wool Fibres - The present invention relates to a process for dyeing fibre materials composed of wool wherein an alkoxylated and quaternized fatty acid amine, preferably a quaternized, ethoxylated oleylamine, is used as a levelling agent. The present compound leads to very uniform dyeings and is very effective in low concentrations. | 06-25-2009 |
Rino Messere, Herzogenrath DE
Patent application number | Description | Published |
---|---|---|
20130319756 | ELECTRICAL FEED-THROUGH SPACER AND CONNECTIVITY - An insulated glazing unit is provided. The unit includes a spacer frame separating a pair of substrates. The spacer frame has a length and a width transverse to the length. The unit further includes a conductive element passing through the width of the spacer frame. The unit further includes a first conductive component within the spacer frame. The first conductive component is in electrical communication with the conductive element. The conductive element is adapted for electrical communication with a second conductive component on a side of the width of the spacer frame opposite the first conductive component. | 12-05-2013 |
20140000191 | SHOULDER SPACER KEY FOR INSULATED GLAZING UNITS | 01-02-2014 |
Rino Messere, Modave BE
Patent application number | Description | Published |
---|---|---|
20080218039 | TRANSPARENT GLAZING AND ITS USE IN A DOOR OF A REFRIGERATED ENCLOSURE, ESPECIALLY ONE HAVING A VACUUM GLAZING UNIT - The subject of the invention is a transparent glazing unit having at least one viewing area and its use in a door of a refrigerated enclosure and more particularly a glazed door, the glazed area of which essentially consists of a vacuum glazing unit. According to the invention the viewing area is combined with an antifrosting absorbent layer deposited on at least one surface of the said area. | 09-11-2008 |
20090114928 | LIGHTING STRUCTURE COMPRISING AT LEAST ONE LIGHT-EMITTING DIODE, METHOD FOR MAKING SAME AND USES THEREOF - A luminous structure based on light-emitting diodes, which includes: a first dielectric element with a substantially plane main face associated with a first electrode; a second dielectric element with a substantially plane main face associated with a second electrode that faces the first electrode and lies in a different plane; at least a first light-emitting diode including a semiconductor chip including, on first and second opposed faces, first and second electrical contacts, the first electrical contact being electrically connected to the first electrode, the second electrical contact being electrically connected to the second electrode, and at least the first element at least partly transmitting radiation within the ultraviolet or in the visible. | 05-07-2009 |
20090323162 | ACTIVE DEVICE HAVING VARIABLE ENERGY/OPTICAL PROPERTIES - The invention relates to an active device having variable energy/light transmission properties ( | 12-31-2009 |
20100062227 | SUBSTRATE WHICH IS PROTECTED AGAINST ORGANIC POLLUTION - The invention relates to a substrate ( | 03-11-2010 |
20110135880 | TEXTURED SUBSTRATE PROVIDED WITH A STACK HAVING THERMAL PROPERTIES - The invention relates to a glass substrate ( | 06-09-2011 |
20110267816 | PANE ASSEMBLY - A pane assembly having an illumination system, comprising at least: | 11-03-2011 |
20140218934 | ILLUMINATED DOUBLE GLAZING - An illuminated window arrangement having insulating glazing is described. The illuminated window arrangement has: | 08-07-2014 |
Rino Micheloni, Turate SM
Patent application number | Description | Published |
---|---|---|
20150143206 | METHOD FOR PERFORMING ERROR CORRECTIONS OF DIGITAL INFORMATION CODIFIED AS A SYMBOL SEQUENCE - A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the 5 transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group. | 05-21-2015 |
Rino Micheloni, Turate IT
Patent application number | Description | Published |
---|---|---|
20090009002 | Voltage switching circuits and methods - A circuit includes a first and a second input terminals and an output terminal. A first circuital branch is connected between the first input terminal and the output terminal, and a second circuital branch connected between the second input terminal and the output terminal. The first and second circuital branches are selectively activatable for coupling the first input terminal with the output terminal and the second input terminal with the output terminal, respectively. The first and second circuital branches each include at least one electronic device having at least a first and a second device terminals. Each electronic device can of sustain voltage differences across the first and second device terminals that are up-limited in absolute value by a first predetermined maximum value lower than the maximum of absolute values of voltage differences between the output terminal and the first input terminal, and between the output terminal and the second input terminal, respectively. | 01-08-2009 |
20090316482 | METHOD OF PROGRAMMING A MULTI-LEVEL MEMORY DEVICE - Embodiments of the present disclosure provide methods and apparatuses related to programming multilevel memory cells of a memory device. Other embodiments may be described and claimed. | 12-24-2009 |
20110167206 | CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE - A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor. | 07-07-2011 |
20110167318 | READING METHOD OF A MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE AND MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE - A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A | 07-07-2011 |
20140036588 | METHOD OF PROGRAMMING A MULTI-LEVEL MEMORY DEVICE - Embodiments of the present disclosure provide methods and apparatuses related to programming multilevel memory cells of a memory device. Other embodiments may be described and claimed. | 02-06-2014 |
20140281800 | SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC DECODING - A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword. | 09-18-2014 |
20140281823 | SYSTEM AND METHOD WITH REFERENCE VOLTAGE PARTITIONING FOR LOW DENSITY PARITY CHECK DECODING - A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword. | 09-18-2014 |
20140281828 | SYSTEM AND METHOD FOR ACCUMULATING SOFT INFORMATION IN LDPC DECODING - A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding. | 09-18-2014 |
Rino Micheloni, Turate (co) IT
Patent application number | Description | Published |
---|---|---|
20090262593 | CIRCUIT AND METHOD FOR RETRIEVING DATA STORED IN SEMICONDUCTOR MEMORY CELLS - A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic. | 10-22-2009 |
Rino Rappuloi, Siena IT
Patent application number | Description | Published |
---|---|---|
20090317420 | Immunogenic compositions for gram positive bacteria such as streptococcus agalactiae - The invention relates to the identification of a new adhesin islands within the genomes of several Group A and Group B | 12-24-2009 |
Rino Rappuoli, Berardenda IT
Patent application number | Description | Published |
---|---|---|
20110104193 | COMBINATION NEISSERIAL COMPOSITIONS - Compositions comprising a first biological molecule from a | 05-05-2011 |
20120135026 | COMBINATION NEISSERIAL COMPOSITIONS - Compositions comprising a first biological molecule from a | 05-31-2012 |
Rino Rappuoli, Vagliagli IT
Patent application number | Description | Published |
---|---|---|
20120135024 | NEISSERIA MENINGITIDIS ANTIGENS AND COMPOSITIONS - The invention provides proteins from | 05-31-2012 |
20120148616 | NEISSERIA MENINGITIDIS ANTIGENS AND COMPOSITIONS - The invention provides proteins from | 06-14-2012 |
20120156236 | NEISSERIA MENINGITIDIS ANTIGENS AND COMPOSITIONS - The invention provides proteins from | 06-21-2012 |
20120164166 | NEISSERIA MENINGITIDIS ANTIGENS AND COMPOSITIONS - The invention provides proteins from | 06-28-2012 |
20150079124 | NEISSERIA MENINGITIDIS ANTIGENS AND COMPOSITIONS - The invention provides proteins from | 03-19-2015 |
20150086582 | NEISSERIA MENINGITIDIS ANTIGENS AND COMPOSITIONS - The invention provides proteins from | 03-26-2015 |
Rino Rappuoli, Casteinuovo Berardenga IT
Patent application number | Description | Published |
---|---|---|
20120237536 | COMBINATION VACCINES AGAINST RESPIRATORY TRACT DISEASES - Influenza, pneumococcus and/or RSV vaccines are administered as a combination vaccine while retaining immunogenic efficacy. This combination simplifies immunisation against these two lower respiratory tract infections. The pneumococcal vaccine ideally includes at least one pneumococcal polypeptide. | 09-20-2012 |
Rino Rappuoli, Castelnuovo Berardena IT
Patent application number | Description | Published |
---|---|---|
20120070456 | POLYPEPTIDE CARRIER PROTEIN - The invention relates to polypeptide carrier proteins that comprise at least five CD4+ T cell epitopes, for conjugation to capsular polysaccharides. The carrier proteins are useful as components of vaccines that can elicit a T-cell dependent immune response. These vaccines are particularly useful to confer protection against infection from encapsulated bacteria in infants between the ages of 3 months and about 2 years. | 03-22-2012 |
Rino Rappuoli, Castelnuoevo Berardenga (siena) IT
Patent application number | Description | Published |
---|---|---|
20090176699 | Inhibitors Based on Fusion, Hr1 and Hr2 Sequences in Bacterial Adhesin - A known surface adhesin (NadA) in | 07-09-2009 |
Rino Stefanutti, Madrid ES
Patent application number | Description | Published |
---|---|---|
20120024970 | Supporting arrangement - Supporting arrangement intended to be arranged in a shoring zone of railway lines ( | 02-02-2012 |
20120160123 | SUPPORT STRUCTURE - Temporary support structure that provisionally supports the railroad tracks ( | 06-28-2012 |