Patent application number | Description | Published |
20080250216 | Protected function calling - Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form. The permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry, in order to assist backward compatibility. | 10-09-2008 |
20090125756 | Trace data timestamping - A data processing apparatus is provided, comprising monitored circuitry for performing activities, trace circuitry for producing a stream of trace elements representative of at least some of these activities, and detection circuitry for detecting the occurrence of a predetermined subset of the activities for which the trace circuitry is producing trace elements. When an activity in that predetermined subset of activities is detected a timing indication is added to the stream of trace elements. Hence, the valuable trace bandwidth- may be preserved, by limiting the trace elements for which a timing indication is added into the trace stream to a predetermined subset of the activities for which trace elements are generated, and the valuable global or relative timing accuracy of those activities represented in the trace stream is retained, without flooding the trace stream with timing indications. | 05-14-2009 |
20090222816 | Data processing apparatus and method for controlling access to secure memory by virtual machines executing on processing circuirty - A data processing apparatus and method are provided for controlling access to secure memory by virtual machines executing on processing circuitry. The processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system is provided for storing data for access by the processing circuitry, the memory system comprising secure memory for storing secure data and non-secure memory for storing non-secure data, the secure memory only being accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. A trusted virtual machine identifier is maintained and managed by the hypervisor software, with the hypervisor software setting the trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. Accordingly, in response to the access request issued by the current virtual machine, the address translation circuitry is only able to cause the modified access request to be issued as a secure access request specifying a physical address within the secure memory if the trusted virtual machine identifier is set. By such an approach, the hypervisor software is able to support multiple virtual machines at least some of which have access to secure memory under conditions controlled by the hypervisor software. | 09-03-2009 |
20090292899 | Data processing apparatus and method for handling address translation for access requests issued by processing circuitry - A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory corresponding to the virtual address. The address translation circuitry references a storage unit, with each entry of the storage unit storing address translation information for one or more virtual addresses. Each entry has a field indicating whether the address translation information is consolidated address translation information or partial address translation information. If when processing an access request, it is determined that the relevant entry in the storage unit provides consolidated address translation information, the address translation circuitry produces a physical address directly from the consolidated address translation information. If on the other hand the relevant entry stores partial address translation information, the address translation circuitry produces an intermediate address from the partial address translation information and then performs the remainder of the multi-stage address translation process. Such an approach provides the performance benefits associated with a consolidated entry mechanism within the storage unit, whilst also allowing certain problem cases to be handled correctly and in an efficient manner. | 11-26-2009 |
20110087809 | Reduced latency barrier transaction requests in interconnects - Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the interconnect circuitry comprising: at least one input for receiving transaction requests from the at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; at least one path for transmitting the transaction requests between the at least one input and the at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some of said transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some of said transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said control circuitry comprises a response signal generator, said response signal generator being responsive to receipt of said barrier transaction request to issue a response signal, said response signal indicating to upstream blocking circuitry that any transaction requests delayed in response to said barrier transaction request can be transmitted further. | 04-14-2011 |
20110087819 | Barrier transactions in interconnects - Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said bather transaction request in said stream of transaction requests; wherein said bather transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained. | 04-14-2011 |
20110125944 | Synchronising activities of various components in a distributed system - An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and issuing requests to said interconnect; a barrier generator for generating barrier transaction requests, the barrier transaction requests indicating to the interconnect that an ordering of at least some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of at least some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request; wherein in response to receipt of a synchronise request querying progress of at least a subset of transaction requests, the initiator device is responsive to action any pending transaction requests within the at least a subset of transaction request and to generate a barrier transaction request at the barrier generator and to issue the barrier transaction request to the interconnect via the at least one port, and in response to receiving a response to the barrier transaction request to issue an acknowledge signal as a response to the synchronise request. | 05-26-2011 |
20110202726 | Apparatus and method for handling data in a cache - A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system. | 08-18-2011 |
20110202739 | Restricting memory areas for an instruction read in dependence upon a hardware mode and a security flag - An apparatus for processing data | 08-18-2011 |
20110202740 | Storing secure page table data in secure and non-secure regions of memory - Apparatus for data processing | 08-18-2011 |
20110213934 | Data processing apparatus and method for switching a workload between first and second processing circuitry - A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being micro-architecturally different from the second processing circuitry. At any point in time, a workload consisting of at least one application and at least one operating system for running that application is performed by one of the first processing circuitry and the second processing circuitry. A switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. During the handover operation, the switch controller causes the source processing circuitry to makes it current architectural state available to the destination processing circuitry, the current architectural state being that state not available from shared memory at a time the handover operation is initiated, and that is necessary for the destination processing circuitry to successfully take over performance of the workload from the source processing circuitry. In addition, the switch controller masks predetermined processor specific configuration information from the at least one operating system such that the transfer of the workload is transparent to that operating system. Such an approach has been found to yield significant energy consumption benefits whilst avoiding complexities associated with providing operating systems with the capability for switching applications between processing circuits. | 09-01-2011 |
20110225397 | Mapping between registers used by multiple instruction sets - A processor | 09-15-2011 |
20110225402 | Apparatus and method for handling exception events - Processing circuitry | 09-15-2011 |
20120042144 | Memory access control - A data processing system | 02-16-2012 |
20130205389 | DATA PROCESSING APPARATUS AND METHOD FOR PROTECTING SECURE DATA AND PROGRAM CODE FROM NON-SECURE ACCESS WHEN SWITCHING BETWEEN SECURE AND LESS SECURE DOMAINS - A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call. | 08-08-2013 |
20130205403 | MAINTAINING SECURE DATA ISOLATED FROM NON-SECURE ACCESS WHEN SWITCHING BETWEEN DOMAINS - A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level. | 08-08-2013 |
20130205413 | DATA PROCESSING APPARATUS AND METHOD USING SECURE DOMAIN AND LESS SECURE DOMAIN - A data processing apparatus | 08-08-2013 |
20130212700 | EXCEPTION HANDLING IN A DATA PROCESSING APPARATUS HAVING A SECURE DOMAIN AND A LESS SECURE DOMAIN - A data processing apparatus and method are provided for handling exceptions, including processing circuitry configured to perform data processing operations in response to program code, said circuitry including exception control circuitry. A plurality of registers are provided including a first and second subsets of registers, and a data store. The data store includes a secure region and a less secure region, wherein the secure region is for storing data accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain. The exception control circuitry performs state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception. Where background processing was performed by the processing circuitry in the secure domain, the exception control circuitry performs additional state saving of the data. | 08-15-2013 |
20140040516 | BARRIER TRANSACTIONS IN INTERCONNECTS - Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained. | 02-06-2014 |
20140040529 | TRANSLATION TABLE CONTROL - Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a hierarchy of translation tables | 02-06-2014 |