Patent application number | Description | Published |
20080216085 | System and Method for Virtual Adapter Resource Allocation - A method, computer program product, and distributed data processing system that enables host software or firmware to allocate virtual resources to one or more system images from a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, is provided. Adapter resource groups are assigned to respective system images. An adapter resource group is exclusively available to the system image to which the adapter resource group assignment was made. Assignment of adapter resource groups may be made per a relative resource assignment or an absolute resource assignment. In another embodiment, adapter resource groups are assigned to system images on a first come, first served basis. | 09-04-2008 |
20080267183 | Infiniband Multicast Operation in an LPAR Environment - A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A preferred embodiment of the present invention allows LPAR “hypervisor” firmware to assume the responsibility for multicast protocol handling and distribution of packets among logical partitions. | 10-30-2008 |
20080270735 | Association of Host Translations that are Associated to an Access Control Level on a PCI Bridge that Supports Virtualization - A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. | 10-30-2008 |
20080307190 | System and Method for Improved Virtual Real Memory - A method for providing virtual real memory includes receiving a request for a memory page from a requestor. A system determines whether the requested memory page is available. In the event the requested memory page is available, the system satisfies the request. In the event the requested memory page is not available, the system generates a page fault interrupt, wherein the page fault interrupt comprises a first page fault correlation number (PFCID) identifying a restorative process, and wherein the restorative process is configured to restore the requested memory page to available memory. The system monitors a plurality of pending processes and determines whether the restorative process is complete. In the event the restorative process is complete, the system notifies the requester that the restorative process is complete. | 12-11-2008 |
20090007118 | Native Virtualization on a Partially Trusted Adapter Using PCI Host Bus, Device, and Function Number for Identification - A mechanism that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to perform I/O transactions using the PCI host bus, device, and function numbers to validate that an I/O transaction originated from the proper host is provided. Additionally, a method for facilitating identification of a transaction source partition is provided. An input/output transaction that is directed to a physical adapter is originated from a system image of a plurality of system images. The host data processing system adds an identifier of the system image to the input/output transaction. The input/output transaction is then conveyed to the physical adapter for processing of the input/output transaction. | 01-01-2009 |
20090089611 | METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR COORDINATING ERROR REPORTING AND RESET UTILIZING AN I/O ADAPTER THAT SUPPORTS VIRTUALIZATION - A method, apparatus, and computer program product are disclosed in a shared processor data processing system for coordinating error reporting for and resetting of a physical I/O adapter that supports virtualization. The physical I/O adapter is virtualized by generating virtual I/O adapters that each represent a portion of the physical I/O adapter. Each one of the virtual I/O adapters is assigned to a different one of client logical partitions. A determination is made regarding whether the physical I/O adapter may have experienced an error. If the physical I/O adapter has experienced an error, all of the client logical partitions are notified about the error and a recovery of the physical I/O adapter is coordinated among all of the client logical partitions by waiting for each client logical partition to acknowledge the error notification before the physical I/O adapter is reset. | 04-02-2009 |
20090106475 | System and Method for Managing Metrics Table Per Virtual Port in a Logically Partitioned Data Processing System - A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to track performance and reliability statistics per virtual upstream and downstream port, thereby allowing a system and network management to be performed at finer granularity than what is possible using conventional physical port statistics, is provided. Particularly, a mechanism of managing per-virtual port performance metrics in a logically partitioned data processing system including allocating a subset of resources of a physical adapter to a virtual adapter of a plurality of virtual adapters is provided. The subset of resources includes a virtual port having an identifier assigned thereto. The identifier of the virtual port is associated with an address of a physical port. A metric table is associated with the virtual port, wherein the metric table includes metrics of operations that target the virtual port. | 04-23-2009 |
20090144462 | Method and System for Fully Trusted Adapter Validation of Addresses Referenced in a Virtual Host Transfer Request - A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation. | 06-04-2009 |
20100042823 | Method, Apparatus, and Product for Providing a Scalable Trusted Platform Module in a Hypervisor Environment - A method, apparatus, and computer program product are described for implementing a trusted computing environment within a data processing system where the data processing system includes a single hardware trusted platform module (TPM). Multiple logical partitions are provided in the data processing system. A unique context is generated for each one of the logical partitions. When one of the logical partitions requires access to the hardware TPM, that partition's context is required to be stored in the hardware TPM. The hardware TPM includes a finite number of storage locations, called context slots, for storing contexts. Each context slot can store one partition's context. Each one of the partitions is associated with one of the limited number of context storage slots in the hardware TPM. At least one of the context slots is simultaneously associated with more than one of the logical partitions. Contexts are swapped into and out of the hardware TPM during runtime of the data processing system so that when ones of the partitions require access to the hardware TPM, their required contexts are currently stored in the hardware TPM. | 02-18-2010 |
20100262727 | Enhanced Memory Migration Descriptor Format and Method - An enhanced migration descriptor migrates a plurality of source sub-pages in a large source page accessible by direct memory access devices. A splitter and selector are integrated into a configuration of a computer. Responsive to a request to migrate a large page containing the plurality of source sub-pages in the source page, the splitter divides a plurality of high order page numbers from a plurality of low order page numbers. The selector selects the high order page number of the large page and creates an enhanced migration descriptor comprising the high order page number and a size of the large page. The selector, by the enhanced migration descriptor, combines the low order page number for a sub-page with the destination address and size of the enhanced migration descriptor to migrate the large page and each of the plurality of sub-pages. | 10-14-2010 |
20110276742 | Characterizing Multiple Resource Utilization Using a Relationship Model to Optimize Memory Utilization in a Virtual Machine Environment - An approach is provided that uses a hypervisor to allocate a shared memory pool amongst a set of partitions (e.g., guest operating systems) being managed by the hypervisor. The hypervisor retrieves memory related metrics from shared data structures stored in a memory, with each of the shared data structures corresponding to a different one of the partitions. The memory related metrics correspond to a usage of the shared memory pool allocated to the corresponding partition. The hypervisor identifies a memory stress associated with each of the partitions with this identification based in part on the memory related metrics retrieved from the shared data structures. The hypervisor then reallocates the shared memory pool amongst the plurality of partitions based on the identified memory stress of the plurality of partitions. | 11-10-2011 |
20120072707 | Scaleable Status Tracking Of Multiple Assist Hardware Threads - A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating. | 03-22-2012 |
20120226946 | Assist Thread Analysis and Debug Mechanism - A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area. | 09-06-2012 |
20120284717 | Assist Thread Analysis and Debug Mechanism - A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area. | 11-08-2012 |
20130139168 | Scaleable Status Tracking Of Multiple Assist Hardware Threads - A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating. | 05-30-2013 |
20140325163 | Cross-Partition Shared Memory Attach for Data Processing Environment - A technique for managing shared memory includes linking address translation data structures used by first and second sharing applications. The first sharing application is managed by a first operating system (OS) and the second sharing application is managed by a second OS that hosts an associated virtual object. Virtual addresses of the first and second sharing applications are bound, based on the linking, to a changeable set of physical addresses that the second OS assigns to the associated virtual object such that the associated virtual object, which is shared by the sharing applications, is pageable by the second OS without permission of the first OS. | 10-30-2014 |