Patent application number | Description | Published |
20080197408 | Isolated quasi-vertical DMOS transistor - Various integrated circuit devices, in particular a quasi-vertical DMOS transistor, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 08-21-2008 |
20080197445 | Isolation and termination structures for semiconductor die - Various integrated circuit devices, including a lateral DMOS transistor, a quasi-vertical DMOS transistor, a junction field-effect transistor (JFET), a depletion-mode MOSFET, and a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 08-21-2008 |
20080197446 | Isolated diode - Various integrated circuit devices, in particular a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 08-21-2008 |
20080197908 | Cascode Power Switch for use in a High-Frequency Power MESFET Buck Switching Power Supply - A cascode power switch for use in a MESFET based switching regulator includes a MOSFET in series with a normally-off MESFET. The cascode power switch is typically connected in between a power source and a node Vx. The node Vx is connected to an output node via an inductor and to ground via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to the battery and to ground. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter. | 08-21-2008 |
20080203520 | Isolation structure for semiconductor integrated circuit substrate - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths. | 08-28-2008 |
20080203543 | Semiconductor integrated circuit substrate containing isolation structures - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths. | 08-28-2008 |
20080203991 | DC-DC Converter that Includes a High Frequency Power MESFET Gate Drive Circuit - A DC-DC converter that includes a high frequency power MESFET gate drive circuit is provided. The gate drive circuits are intended to be used in switching regulators where at least one switching device is an N-channel MESFET. For regulators of this type, the gate drive circuits provide gate drive at the correct voltage to ensure that MESFETs are neither under driven (resulting in incorrect circuit operation) nor over driven (resulting in MESFET damage or excess current or power loss). | 08-28-2008 |
20080210980 | Isolated CMOS transistors - Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 09-04-2008 |
20080213972 | Processes for forming isolation structures for integrated circuit devices - Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 09-04-2008 |
20080217662 | Space-efficient package for laterally conducting device - Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package. | 09-11-2008 |
20080217699 | Isolated Bipolar Transistor - An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains the bipolar transistor. The collector of the bipolar transistor may comprise the floor isolation region. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 09-11-2008 |
20080217729 | Isolation structures for integrated circuit devices - An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 09-11-2008 |
20080230812 | Isolated junction field-effect transistor - Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 09-25-2008 |
20080237656 | Isolated junction field-effect transistor - An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. An isolated junction field-effect transistor is formed in the isolated pocket. | 10-02-2008 |
20080237704 | Isolated trench MOSFET - An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket. | 10-02-2008 |
20080237706 | Lateral MOSFET - A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET may be drain-centric, with the source region and an optional dielectric-filled trench surrounding the drain region. | 10-02-2008 |
20080237782 | Isolated rectifier diode - An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region. | 10-02-2008 |
20080237783 | Isolated bipolar transistor - A bipolar transistor is formed in an isolation structure comprising a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. | 10-02-2008 |
20080252372 | Power-MOSFETs with Improved Efficiency for Multi-channel Class-D Audio Amplifiers and Packaging Thereof - A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (V | 10-16-2008 |
20080254592 | Method of forming isolation structure for semiconductor integrated circuit substrate - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths. | 10-16-2008 |
20080290449 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 11-27-2008 |
20080290450 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 11-27-2008 |
20080290451 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 11-27-2008 |
20080290452 | Trench-constrained isolation diffusion for integrated circuit die - A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achieve deep diffusions with a minimal thermal budget. | 11-27-2008 |
20080290911 | MOSFET gate drive with reduced power loss - A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A feedback circuit may be used to assure that the magnitude of current in the power MOSFET in its low-current condition is correct. Alternatively, a trimming process may be used to correct the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition. | 11-27-2008 |
20080291711 | Step-down switching regulator with freewheeling diode - A freewheeling DC/DC step-down converter includes a high-side MOSFET, an inductor and an output capacitor connected between the input voltage and ground. A freewheeling clamp, which includes a freewheeling MOSFET and diode, is connected across the inductor. When the high-side MOSFET is turned off, a current circulates through the inductor and freewheeling clamp rather than to ground, improving the efficiency of the converter. The converter has softer diode recovery and less voltage overshoot and noise than conventional Buck converters and features unique benefits during light-load conditions. | 11-27-2008 |
20080293214 | Method of fabricating trench-constrained isolation diffusion for semiconductor devices - A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achive deep diffusions with a minimal thermal budget. | 11-27-2008 |
20090010035 | Boost and up-down switching regulator with synchronous freewheeling MOSFET - A freewheeling MOSFET is connected in parallel with the inductor in a switched DC/DC converter. When the freewheeling MOSFET is turned on during the switching operation of the converter, while the low-side and energy transfer MOSFETs are turned off, the inductor current circulates or “freewheels” through the freewheeling MOSFET. The frequency of the converter is thereby made independent of the lengths of the magnetizing and energy transfer stages, allowing far greater flexibility in operating and converter and overcoming numerous problems associated with conventional DC/DC converters. For example, the converter may operate in either step-up or step-down mode and may even transition for one mode to the other as the values of the input voltage and desired output voltage vary. | 01-08-2009 |
20090032876 | ESD protection for bipolar-CMOS-DMOS integrated circuit devices - An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage. | 02-05-2009 |
20090034136 | ESD protection for bipolar-CMOS-DMOS integrated circuit devices - An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage. | 02-05-2009 |
20090034137 | ESD protection for bipolar-CMOS-DMOS integrated circuit devices - An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage. | 02-05-2009 |
20090039869 | Cascode Current Sensor For Discrete Power Semiconductor Devices - A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss. | 02-12-2009 |
20090039947 | Time-Multiplexed-Capacitor DC/DC Converter with Multiple Outputs - A multiple output DC-to-DC voltage converter using a new time-multiplexed-capacitor converter algorithm and related circuit topologies is herein disclosed. One embodiment of this invention includes a flying capacitor, a first output node, a second output node, and a switching network. The switching network configured to provide the following modes of circuit operation: 1) a first mode where the positive electrode of the flying capacitor is connected to an input voltage and the negative electrode of the flying capacitor is connected to ground; 2) a second mode where the negative electrode of the flying capacitor is connected to the input voltage and the positive electrode of the flying capacitor is connected to the first output node; and 3) a third mode where the positive electrode of the flying capacitor is connected to ground and the negative electrode of the flying capacitor is connected to the second output node. | 02-12-2009 |
20090040794 | Time-Multiplexed Multi-Output DC/DC Converters and Voltage Regulators - A boost switching converter with multiple outputs includes an inductor is connected between an input supply (typically a battery) and a node V | 02-12-2009 |
20090045788 | High Voltage SEPIC Converter - A SEPIC converter with over-voltage protection includes a high-side inductor that connects a node V | 02-19-2009 |
20090059630 | High-efficiency DC/DC voltage converter including capacitive switching pre-converter and down inductive switching post-regulator - A DC/DC converter includes a pre-converter stage, which may include a charge pump, and a post-regulator stage, which may include a Buck converter. The duty factor of the post-regulator stage is controlled by a feedback path that extends from the output terminal of the DC/DC converter to an input terminal in the post-regulator stage. The pre-converter steps the input DC voltage up or down by a positive or negative integral or fractional value, and the post-regulator steps the voltage down by a variable amount depending on the duty factor at which the post-regulator is driven. The converter overcomes the problems of noise glitches, poor regulation, and instability, even near unity input-to-output voltage conversion ratios. | 03-05-2009 |
20090102439 | Step-up DC/DC voltage converter with improved transient current capability - A DC/DC voltage converter includes an inductive switching voltage regulator and a capacitive charge pump connected in series between the input and output terminals of the converter. The charge pump has a second input terminal connected to the input terminal of the converter. This reduces the series resistance in the current path by which charge is transferred from the capacitor in the charge pump to the output capacitor and thereby improves the ability of the converter to respond to rapid changes in current required by the load. | 04-23-2009 |
20090236683 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 09-24-2009 |
20100001703 | Programmable Step-Up Switching Voltage Regulators with Adaptive Power MOSFETs - A step-up switching voltage regulator includes an inductor connected between an input voltage and a node Vx, M low-side switches connected between the node Vx and a ground voltage and N synchronous rectifiers connected between the node Vx and an output node. An interface circuit that decodes a control signal to identify: 1) a subset (m) of the low-side switches, 2) a subset (n) of the synchronous rectifiers, and 3) a reference voltage V | 01-07-2010 |
20100001704 | Programmable Step-Down Switching Voltage Regulators with Adaptive Power MOSFETs - A step-down switching voltage regulator includes M high-side switches connected between an input voltage and a node; N synchronous rectifiers connected between the node Vx and a ground voltage and an inductor connected between an input voltage and a node Vx and an inductor connected between the node Vx and an output node. An interface circuit decodes a control signal to identify: 1) a subset (m) of the high-side switches, 2) a subset (n) of the synchronous rectifiers. A control circuit drives the high-side switches and synchronous rectifiers in a repeating sequence that includes an inductor charging phase where the high-side switches in the subset m are activated to connect the node Vx to the input voltage; and an inductor discharging phase where the synchronous rectifiers in the subset n are activated to connect the node Vx to the ground voltage. | 01-07-2010 |
20100002473 | Multiple-Output Dual-Polarity DC/DC Converters and Voltage Regulators - A multi-output dual polarity inductive boost converter includes an inductor, a first output node, a second output node, and a switching network, the switching network configured to provide the following modes of circuit operation: a first mode where the positive electrode of the inductor is connected to an input voltage and the negative electrode of the inductor is connected to ground; 2) a second mode the negative electrode of the inductor is connected to ground and the positive electrode of the inductor is connected in sequence to one or more of the fourth and fifth output nodes; and 3) a third mode where the positive electrode of the inductor is connected to the input voltage and the negative electrode of the inductor is connected in sequence to one or more of the first, second and third output nodes. | 01-07-2010 |
20100055864 | Method of forming isolation structure for semiconductor integrated circuit substrate - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths. | 03-04-2010 |
20100133611 | Isolated transistor - A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. | 06-03-2010 |
20110012196 | Isolated drain-centric lateral MOSFET - A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET is drain-centric, with the source region and a dielectric-filled trench surrounding the drain region. | 01-20-2011 |
20110018593 | MOSFET gate drive with reduced power loss - A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A trimming process is used to adjust the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition. | 01-27-2011 |
20110201171 | Processes For Forming Isolation Structures For Integrated Circuit Devices - Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 08-18-2011 |
20110202787 | Single Wire Serial Interface - A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin. | 08-18-2011 |
20110221421 | Method Of Sensing Magnitude Of Current Through Semiconductor Power Device - A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss. | 09-15-2011 |
20110248691 | Method Of Starting DC/DC Converter Using Synchronous Freewheeling MOSFET - A DC/DC converter including an inductor and a capacitor is started by connecting an input voltage to the inductor and shunting a current around the inductor so as to pre-charge the capacitor to a predetermined voltage. | 10-13-2011 |
20110260246 | Isolated Transistor - A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. | 10-27-2011 |
20110291254 | SEMICONDUCTOR DEVICE PACKAGE FEATURING ENCAPSULATED LEADFRAME WITH PROJECTING BUMPS OR BALLS - Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with at least one die through electrically conducting bumps or balls and electrically conducting ribbons. Embodiments of the present invention may permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint. | 12-01-2011 |
20130027980 | DC/DC Converter Using Synchronous Freewheeling MOSFET - A freewheeling MOSFET is connected in parallel with the inductor in a switched DC/DC converter. When the freewheeling MOSFET is turned on during the switching operation of the converter, while the low-side and energy transfer MOSFETs are turned off, the inductor current circulates or “freewheels” through the freewheeling MOSFET. The frequency of the converter is thereby made independent of the lengths of the magnetizing and energy transfer stages, allowing far greater flexibility in operating and converter and overcoming numerous problems associated with conventional DC/DC converters. In one embodiment the freewheeling MOSFET is an N-channel MOSFET with its body connected to circuit ground and not shorted to either its source or its drain. | 01-31-2013 |
20130043572 | Bump-On-Leadframe Semiconductor Package With Low Thermal Resistance - In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface. A structure including arrays of thermal vias may be used to transfer the heat from the semiconductor substrate to the metal bump | 02-21-2013 |
20130043573 | Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores - A semiconductor die is solder bump-bonded to a leadframe or circuit board using solder balls having cores made of a material with a melting temperature higher than the melting temperature of the solder to ensure that in the finished structure the die is parallel to the leadframe or circuit board. | 02-21-2013 |
20130043574 | Multi-Die Semiconductor Package With One Or More Embedded Die Pads - To avoid shorts between adjacent die pads in mounting a multi-die semiconductor package to a printed circuit board (PCB), one of the die pads is embedded in the polymer capsule, while the other die pad is exposed at the bottom of the package to provide a thermal escape path to the PCB. This arrangement is particularly useful when one of the dice in a multi-die package generates more heat than another die in the package. | 02-21-2013 |
20130043595 | Semiconductor Package Containing Silicon-On-Insulator Die Mounted In Bump-On-Leadframe Manner To Provide Low Thermal Resistance - Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure. | 02-21-2013 |
20130082604 | Low Cost LED Driver With Integral Dimming Capability - A distributed system for driving strings of series-connected LEDs for backlighting, display and lighting applications includes multiple intelligent satellite LED driver ICs connected to a an interface IC via serial bus. The interface IC translates information obtained from a host microcontroller into instructions for the satellite LED driver ICs pertaining to such parameters as duty factor, current levels, phase delay and fault settings. Fault conditions in the LED driver ICs can be transmitted back to the interface IC. An analog current sense feedback system which also links the LED driver ICs determines the supply voltage for the LED strings. | 04-04-2013 |
20130082609 | Low Cost LED Driver With Integral Dimming Capability - A distributed system for driving strings of series-connected LEDs for backlighting, display and lighting applications includes multiple intelligent satellite LED driver ICs connected to a an interface IC via serial bus. The interface IC translates information obtained from a host microcontroller into instructions for the satellite LED driver ICs pertaining to such parameters as duty factor, current levels, phase delay and fault settings. Fault conditions in the LED driver ICs can be transmitted back to, the interface IC. An analog current sense feedback system which also links the LED driver ICs determines the supply voltage for the LED strings. | 04-04-2013 |
20130082614 | Low Cost LED Driver With Integral Dimming Capability - A distributed system for driving strings of series-connected LEDs for backlighting, display and lighting applications includes multiple intelligent satellite LED driver ICs connected to a an interface IC via serial bus. The interface IC translates information obtained from a host microcontroller into instructions for the satellite LED driver ICs pertaining to such parameters as duty factor, current levels, phase delay and fault settings. Fault conditions in the LED driver ICs can be transmitted back to the interface IC. An analog current sense feedback system which also links the LED driver ICs determines the supply voltage for the LED strings. | 04-04-2013 |
20130082615 | Low Cost LED Driver With Integral Dimming Capability - A distributed system for driving strings of series-connected LEDs for backlighting, display and lighting applications includes multiple intelligent satellite LED driver ICs connected to a an interface IC via serial bus. The interface IC translates information obtained from a host microcontroller into instructions for the satellite LED driver ICs pertaining to such parameters as duty factor, current levels, phase delay and fault settings. Fault conditions in the LED driver ICs can be transmitted back to the interface IC. An analog current sense feedback system which also links the LED driver ICs determines the supply voltage for the LED strings. | 04-04-2013 |
20130099682 | Low Cost LED Driver With Improved Serial Bus - An LED driver IC for driving external strings of LEDs comprises a prefix register and a data register connected in series with each other and with the prefix and data registers in other driver ICs. The prefix and data registers of the driver ICs are connected in a daisy chain arrangement with an interface IC. The interface IC loads data identifying a functional latch into the prefix register and data defining a functional condition into the data register of each driver IC. The data in the data register is then transferred to the functional latch to control the functional condition within the LED driver IC. | 04-25-2013 |
20130099701 | Low Cost LED Driver With Improved Serial Bus - An LED driver IC for driving external strings of LEDs comprises a prefix register and a data register connected in series with each other and with the prefix and data registers in other driver ICs. The prefix and data registers of the driver ICs are connected in a daisy chain arrangement with an interface IC. The interface IC loads data identifying a functional latch into the prefix register and data defining a functional condition into the data register of each driver IC. The data in the data register is then transferred to the functional latch to control the functional condition within the LED driver IC. | 04-25-2013 |
20130099702 | Low Cost LED Driver With Improved Serial Bus - An LED driver IC for driving external strings of LEDs comprises a prefix register and a data register connected in series with each other and with the prefix and data registers in other driver ICs. The prefix and data registers of the driver ICs are connected in a daisy chain arrangement with an interface IC. The interface IC loads data identifying a functional latch into the prefix register and data defining a functional condition into the data register of each driver IC. The data in the data register is then transferred to the functional latch to control the functional condition within the LED driver IC. | 04-25-2013 |
20130119955 | High Voltage SEPIC Converter - A SEPIC converter with over-voltage protection includes a high-side inductor that connects a node V | 05-16-2013 |
20130147370 | Serial Lighting Interface With Embedded Feedback - A system for controlling multiple strings of LEDs includes a group of LED driver ICs, each of which includes a current sense feedback (CSFB) sample latch for storing a digital representation of the forward-voltage drop across a controlled LED string. Each CSFB latch is coupled to a register within a serial lighting interface (SLI) bus that both originates and terminates at an interface IC. As the data on the SLI bus is shifted into the interface IC, the interface IC selects the CSFB word that represents the highest forward-voltage drop of any of the controlled LED strings, which is then used by the interface IC to generate a CSFB signal for setting the appropriate supply voltage for the controlled LED strings. | 06-13-2013 |
20130147371 | Serial Lighting Interface With Embedded Feedback - A system for controlling multiple strings of LEDs includes a group of LED driver IC's, each of which includes a current sense feedback (CSFB) sample latch for storing a digital representation of the forward-voltage drop across a controlled LED string. Each CSFB latch is coupled to a register within a serial lighting interface (SLI) bus that both originates and terminates at an interface IC. As the data on the SLI bus is shifted into the interface IC, the interface IC selects the CSFB word that represents the highest forward-voltage drop of any of the controlled LED strings, which is then used by the interface IC to generate a CSFB signal for setting the appropriate supply voltage for the controlled LED strings. | 06-13-2013 |
20130147372 | Serial Lighting Interface With Embedded Feedback - A system for controlling multiple strings of LEDs includes a group of LED driver ICs, each of which includes a current sense feedback (CSFB) sample latch for storing a digital representation of the forward-voltage drop across a controlled LED string. Each CSFB latch is coupled to a register within a serial lighting interface (SLI) bus that both originates and terminates at an interface IC. As the data on the SLI bus is shifted into the interface IC, the interface IC selects the CSFB word that represents the highest forward-voltage drop of any of the controlled LED strings, which is then used by the interface IC to generate a CSFB signal for setting the appropriate supply voltage for the controlled LED strings. | 06-13-2013 |
20130147375 | Serial Lighting Interface With Embedded Feedback - A system for controlling multiple strings of LEDs includes a group of LED driver ICs, each of which includes a current sense feedback (CSFB) sample latch for storing a digital representation of the forward-voltage drop across a controlled LED string. Each CSFB latch is coupled to a register within a serial lighting interface (SLI) bus that both originates and terminates at an interface IC. As the data on the SLI bus is shifted into the interface IC, the interface IC selects the CSFB word that represents the highest forward-voltage drop of any of the controlled LED strings, which is then used by the interface IC to generate a CSFB signal for setting the appropriate supply voltage for the controlled LED strings. | 06-13-2013 |
20130162336 | Time-Multiplexed-Capacitor DC/DC Converter With Multiple Outputs - A multiple output DC-to-DC voltage converter using a new time-multiplexed-capacitor converter algorithm and related circuit topologies is herein disclosed. One embodiment of this invention includes a flying capacitor, a first output node, a second output node, and a switching network. The switching network configured to provide the following modes of circuit operation: 1) a first mode where the positive electrode of the flying capacitor is connected to an input voltage and the negative electrode of the flying capacitor is connected to ground; 2) a second mode where the negative electrode of the flying capacitor is connected to the input voltage and the positive electrode of the flying capacitor is connected to the first output node; and 3) a third mode where the positive electrode of the flying capacitor is connected to ground and the negative electrode of the flying capacitor is connected to the second output node. | 06-27-2013 |
20130200952 | POWER MOSFETS WITH IMPROVED EFFICIENCY FOR MULTI-CHANNEL CLASS D AUDIO AMPLIFIERS AND PACKAGING THEREFOR - A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (Vcc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits. | 08-08-2013 |
20130252377 | Process For Fabricating Multi-Die Semiconductor Package With One Or More Embedded Die Pads - To avoid shorts between adjacent die pads in mounting, a multi-die semiconductor package to a printed circuit board (PCB), one of the die pads is embedded in the polymer capsule, while the other die pad is exposed at the bottom of the package to provide a thermal escape path to the PCB. This arrangement is particularly useful when one of the dice in a multi-die package generates more heat than another die in the package. A process for fabricating the package includes a partial etch that defines the bottom surface of the embedded die pad and may include a through-etch that leaves one or more of the contacts or leads integrally connected to the embedded die pad. | 09-26-2013 |
20140035133 | SEMICONDUCTOR PACKAGE CONTAINING SILICON-ON-INSULATOR DIE MOUNTED IN BUMP-ON-LEADFRAME MANNER TO PROVIDE LOW THERMAL RESISTANCE - Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure. | 02-06-2014 |
20140089722 | Single Wire Serial Interface - A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin. | 03-27-2014 |
20140128941 | Phototherapy System And Process Including Dynamic LED Driver With Programmable Waveform - A phototherapy or photobiomodulation process employing the application of electromagnetic radiation (EMR) to a living organism, typically a human being. The EMR is generated by one or more strings of LEDs and is programmed to emit one or more wavelengths, typically in the visible and infrared portions of the spectrum, the EMR in each wavelength being delivered in pulses having specified on-times, off-times, photoexcitation frequencies, duty factors, phase delays, and power amplitudes. A system for providing such EMR includes a microcontroller having a pattern library of algorithms, each of which defines a particular sequence of synthesized pulses, and an application pad, preferably flexible, containing the LED strings. | 05-08-2014 |
20140203870 | POWER MOSFETS WITH IMPROVED EFFICIENCY FOR MULTI-CHANNEL CLASS D AUDIO AMPLIFIERS AND PACKAGING THEREFOR - A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including, four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (Vcc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits. | 07-24-2014 |
20140257833 | Cloud Based System For Remote Medical Checkup And Physician Managed Biometric Data - In a remote medical checkup system, a patient's symptoms are transmitted for review to a medical service provider, the medical service provider prescribes diagnostic tests using an identified biometric sensor, the tests are performed by the patient, and the results of the tests are transmitted back to the medical service provider, all using a cloud-based server or other storage device. With this system, the tests are performed and the results reported promptly, without the patient having to schedule a visit to the office of the medical service provider. | 09-11-2014 |
20140285178 | SYSTEM AND METHOD OF SENSING CURRENT IN A POWER SEMICONDUCTOR DEVICE - A current sensor to be connected in series with a power semiconductor device between a voltage supply terminal and ground. The current sensor includes a first terminal to be coupled to the power semiconductor device, a second terminal to be coupled to one of the voltage supply terminal and ground, and a current mirror. The current mirror includes a first MOSFET and a second MOSFET each having a source, a drain, and a gate. The source of the first MOSFET is connected to the source of the second MOSFET and to the second terminal, the drain of the first MOSFET is connected to the first terminal, and the gate of the first MOSFET is connected to the gate of the second MOSFET. | 09-25-2014 |
20140306330 | Low Profile Leaded Semiconductor Package - In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed. | 10-16-2014 |
20140354251 | MULTIPLE OUTPUT DUAL-POLARITY BOOST CONVERTER - A dual-polarity multiple-output boost converter that includes an inductor coupled in series between a high-side switch and a low-side switch. A first terminal of the inductor is coupled to an output of the high-side switch and the second terminal of the inductor is coupled to an input of the low side switch, with an output of low-side switch being coupled to a reference terminal. A plurality of outputs provide a plurality of output voltages, including a first plurality of outputs to provide a first plurality of different output voltages having a first polarity and at least one second output to provide at least one second output voltage having a second polarity opposite the first polarity. A control circuit is coupled to the high-side switch and the low-side switch to control an on-time of the high-side switch and the low-side switch. | 12-04-2014 |
20150015325 | MULTIPLE OUTPUT CHARGE PUMP WITH MULTIPLE FLYING CAPACITORS - A multiple output charge pump that includes a first flying capacitor, a second flying capacitor, a first output node, a second output node, and a switching network. The first output node is configured to provide a first voltage, and the second output node is distinct from the first output node and is configured to provide a second voltage, different than the first voltage. The switching network is configured to provide a first mode of operation in which the first and second flying capacitors are connected in one of in series with one another between an input voltage and ground or in parallel with one another between the input voltage and ground, a second mode of operation in which the first and second flying capacitors are connected in parallel with one another between ground and the second output node, and a third mode of operation. | 01-15-2015 |
20150028771 | SINGLE WIRE SERIAL INTERFACE - A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin. | 01-29-2015 |
20150028777 | SINGLE WIRE SERIAL INTERFACE UTILIZING COUNT OF ENCODED CLOCK PULSES WITH RESET - A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin. | 01-29-2015 |
20150035455 | SINGLE WIRE SERIAL INTERFACE - A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin. | 02-05-2015 |