Patent application number | Description | Published |
20110261500 | BACK END OF LINE METAL-TO-METAL CAPACITOR STRUCTURES AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for capacitor structures. One embodiment of a capacitor structure comprises a plurality of consecutive metal layers and another metal layer. Each via layer of a plurality of via layers is interposed between metal layers of the plurality of metal layers. The plurality of metal layers and the plurality of via layers are cooperatively configured to provide a first plurality of vertical conductive structures corresponding to a first electrode and a second plurality of vertical conductive structures corresponding to a second electrode. The plurality of consecutive metal layers form a plurality of vertically-aligned regions and provide intralayer electrical interconnections among the first plurality of vertical conductive structures. The first metal layer provides an intralayer electrical interconnection among the second plurality of vertical conductive structures, wherein each vertically-aligned region has a vertical conductive structure of the second plurality of vertical conductive structures disposed therein. | 10-27-2011 |
20110299337 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-08-2011 |
20130270606 | Semiconductor Device with Integrated Breakdown Protection - A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path. | 10-17-2013 |
20130341717 | Semiconductor Device with Floating RESURF Region - A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap. | 12-26-2013 |
20140001473 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH SOURCE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001477 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH DRAIN AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001546 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH A CURRENT CARRYING REGION AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001548 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140001549 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140375370 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-25-2014 |