Patent application number | Description | Published |
20100070319 | ADAPTIVE CONFIGURATION MANAGEMENT SYSTEM - An automated configuration management system (ACMS) oversees resources of a virtualized ecosystem by establishing a baseline configuration (including, e.g., security controls) for the resources; and, repeatedly, monitoring and collecting data from the resources, analyzing the data collected, making recommendations concerning configuration changes for the resources of the virtualized ecosystem based on the analysis, and either adopting and implementing the recommendations or not, wherein new states of the virtualized ecosystem and reactions to recommended changes are observed and applied in the form of new recommendations, and/or as adjustments to the baseline. The recommendations may be implemented automatically or only upon review by an administrator before being implemented or not. The various data may be analyzed according to benchmarks established for security and compliance criteria of the resources of the virtualized ecosystem, for example static/pre-defined or dynamically derived benchmarks/best practices. | 03-18-2010 |
20100071035 | METHODS AND SYSTEMS FOR SECURELY MANAGING VIRTUALIZATION PLATFORM - Virtualization platforms and management clients therefor are communicatively coupled to one another via a control layer logically disposed therebetween. The control layer is configured to proxy virtualization management commands from the management clients to the virtualization platforms, but only after successful authentication of users (which may include automated agents and processes) issuing those commands and privileges of those users as defined by access control information accessible to the control layer. The control layer may be instantiated as an application running on a physical appliance logically interposed between the virtualization platforms and management clients, or a software package running on dedicated hardware logically interposed between the virtualization platforms and management clients, or as an application encapsulated in a virtual machine running on a compatible virtualization platform logically interposed between the virtualization platforms and management clients. | 03-18-2010 |
20100169948 | INTELLIGENT SECURITY CONTROL SYSTEM FOR VIRTUALIZED ECOSYSTEMS - Resources of a virtualized ecosystem are intelligently secured by defining and analyzing object handling security control information for one or more logical resources in the virtualized ecosystem and deriving therefrom object properties for each of the logical resources involved in the execution of a virtual machine in any given context within the virtualized ecosystem. | 07-01-2010 |
20120036561 | METHODS AND SYSTEMS FOR SECURELY MANAGING VIRTUALIZATION PLATFORM - Virtualization platforms and management clients therefor are communicatively coupled to one another via a control layer logically disposed therebetween. The control layer is configured to proxy virtualization management commands from the management clients to the virtualization platforms, but only after successful authentication of users (which may include automated agents and processes) issuing those commands and privileges of those users as defined by access control information accessible to the control layer. The control layer may be instantiated as an application running on a physical appliance logically interposed between the virtualization platforms and management clients, or a software package running on dedicated hardware logically interposed between the virtualization platforms and management clients, or as an application encapsulated in a virtual machine running on a compatible virtualization platform logically interposed between the virtualization platforms and management clients. | 02-09-2012 |
20120204267 | ADAPTIVE CONFIGURATION MANAGEMENT SYSTEM - An automated configuration management system (ACMS) oversees resources of a virtualized ecosystem by establishing a baseline configuration (including, e.g., security controls) for the resources; and, repeatedly, monitoring and collecting data from the resources, analyzing the data collected, making recommendations concerning configuration changes for the resources of the virtualized ecosystem based on the analysis, and either adopting and implementing the recommendations or not, wherein new states of the virtualized ecosystem and reactions to recommended changes are observed and applied in the form of new recommendations, and/or as adjustments to the baseline. The recommendations may be implemented automatically or only upon review by an administrator before being implemented or not. The various data may be analyzed according to benchmarks established for security and compliance criteria of the resources of the virtualized ecosystem, for example static/pre-defined or dynamically derived benchmarks/best practices. | 08-09-2012 |
20130138971 | INTELLIGENT SECURITY CONTROL SYSTEM FOR VIRTUALIZED ECOSYSTEMS - Resources of a virtualized ecosystem are intelligently secured by defining and analyzing object handling security control information for one or more logical resources in the virtualized ecosystem and deriving therefrom object properties for each of the logical resources involved in the execution of a virtual machine in any given context within the virtualized ecosystem. | 05-30-2013 |
Patent application number | Description | Published |
20090256174 | DEVICE STRUCTURES FOR A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR MANUFACTURED USING A HYBRID ORIENTATION TECHNOLOGY WAFER AND DESIGN STRUCTURES FOR A HIGH VOLTAGE INTEGRATED CIRCUIT - Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer. | 10-15-2009 |
20090258464 | METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER - Methods for manufacturing a high voltage junction field effect transistor. The method includes forming an opening extending from a top surface of a device layer of a hybrid orientation technology (HOT) wafer through the device layer and an insulating layer to expose a portion of a bulk layer, and filling the opening with epitaxial semiconductor material having the crystalline orientation of the bulk layer. The method further includes forming first and second p-n junctions in the epitaxial semiconductor material that are arranged in depth within the epitaxial semiconductor material between the second semiconductor layer and the top surface of the first semiconductor layer. | 10-15-2009 |
20110309471 | TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance C | 12-22-2011 |
20120112244 | VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening. | 05-10-2012 |
20120221987 | VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening. | 08-30-2012 |
20120306014 | STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE - A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate. | 12-06-2012 |
20120326766 | Silicon Controlled Rectifier with Stress-Enhanced Adjustable Trigger Voltage - Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR. | 12-27-2012 |
20130009280 | BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES - Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together. | 01-10-2013 |
20130119508 | BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS - Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process. | 05-16-2013 |
20130140668 | Forming Structures on Resistive Substrates - A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices. | 06-06-2013 |
20130147017 | BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES - Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together. | 06-13-2013 |
20130187198 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE - A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer. | 07-25-2013 |
20130313607 | Silicon Controlled Rectifier With Stress-Enhanced Adjustable Trigger Voltage - Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR. | 11-28-2013 |
20140030861 | STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE - A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate. | 01-30-2014 |
20140203894 | NOTCH FILTER STRUCTURE WITH OPEN STUBS IN SEMICONDUCTOR SUBSTRATE AND DESIGN STRUCTURE - On-chip millimeter wave (mmW) notch filters with via stubs, methods of manufacture and design structures are disclosed. The notch filter includes a signal line comprising a metal trace line connected to a metal via stub partially extending into a semiconductor substrate. The notch filter further includes a defected ground plane connected to at least one or more additional metal via stubs partially extending into the semiconductor substrate. | 07-24-2014 |
20140213036 | FORMING STRUCTURES ON RESISTIVE SUBSTRATES - A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices. | 07-31-2014 |
20140264341 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer. | 09-18-2014 |
20140327111 | TRENCH ISOLATION STRUCTURES AND METHODS FOR BIPOLAR JUNCTION TRANSISTORS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region. | 11-06-2014 |
20150021738 | BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer. | 01-22-2015 |
20150035011 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE - Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer. | 02-05-2015 |
20150053982 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE - Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer. | 02-26-2015 |
20150060950 | TRENCH ISOLATION STRUCTURES AND METHODS FOR BIPOLAR JUNCTION TRANSISTORS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region. | 03-05-2015 |
20150137185 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH AN AIRGAP BETWEEN THE EXTRINSIC BASE AND COLLECTOR - Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface. | 05-21-2015 |
20150194510 | SELF-ALIGNED EMITTER-BASE-COLLECTOR BIPOLAR JUNCTION TRANSISTORS WITH A SINGLE CRYSTAL RAISED EXTRINSIC BASE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench. | 07-09-2015 |
20150311324 | SELF-ALIGNED EMITTER-BASE-COLLECTOR BIPOLAR JUNCTION TRANSISTORS WITH A SINGLE CRYSTAL RAISED EXTRINSIC BASE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench. | 10-29-2015 |
20160049503 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer. | 02-18-2016 |
20160087073 | BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer. | 03-24-2016 |
20160104770 | PROFILE CONTROL OVER A COLLECTOR OF A BIPOLAR JUNCTION TRANSISTOR - Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench. | 04-14-2016 |
Patent application number | Description | Published |
20120045439 | TUMOR MARKERS AND METHODS OF USE THEREOF - The invention provides newly identified proteins as markers for the detection of tumors, or as targets for their treatment, particularly of tumors affecting lung, colon, breast, ovary; affinity ligands capable of selectively interacting with the newly identified markers; methods of screening a tissue sample for malignancy, for determining the presence of a tumor in a subject and for screening a test compound as an antitumor candidate; a diagnostic kit. | 02-23-2012 |
20120322074 | Prostate Tumor Markers and Methods of Use Thereof - Newly identified proteins as markers for the detection of prostate tumors, or as targets for their therapeutic treatment, affinity ligands capable of selectively interacting with said markers as well as methods for tumor diagnosis and therapy using the same. | 12-20-2012 |
20120322075 | Lung Tumor Markers and Methods of Use Thereof - Newly identified proteins as markers for the detection of lung tumors, or as therapeutic targets for their treatment, affinity ligands capable of selectively interacting with the newly identified markers and methods for tumor diagnosis and therapy using such ligands. | 12-20-2012 |
20130004955 | Ovary Tumor Markers and Methods of Use Thereof - Newly identified proteins as markers for the detection of ovary tumors, or as therapeutic targets for treatment thereof; affinity ligands capable of selectively interacting with the newly identified markers, methods for tumor diagnosis and therapy using the same. | 01-03-2013 |
20130017546 | Breast Tumor Markers and Methods of Use ThereofAANM Grifantini; RenataAACI SienaAACO ITAAGP Grifantini; Renata Siena ITAANM Pileri; PieroAACI SienaAACO ITAAGP Pileri; Piero Siena ITAANM Campagnoli; SusannaAACI SienaAACO ITAAGP Campagnoli; Susanna Siena ITAANM Grandi; AlbertoAACI SienaAACO ITAAGP Grandi; Alberto Siena ITAANM Parri; MatteoAACI SienaAACO ITAAGP Parri; Matteo Siena ITAANM Pierleoni; AndreaAACI SienaAACO ITAAGP Pierleoni; Andrea Siena ITAANM Nogarotto; RenzoAACI SienaAACO ITAAGP Nogarotto; Renzo Siena IT - Newly identified proteins as markers for the detection of breast tumors, or as therapeutic targets for treatment thereof; affinity ligands capable of selectively interacting with the newly identified markers, as well as methods for tumor diagnosis and therapy using such ligands. | 01-17-2013 |
20130022983 | Colon and Rectal Tumor Markers and Methods of Use Thereof - Newly identified proteins as markers for the detection of colon and rectal tumors, or as therapeutic targets for treatment thereof; affinity ligands capable of selectively interacting with the newly identified markers, as well as methods for tumor diagnosis and therapy using such ligands. | 01-24-2013 |
20130137106 | Tumor Marker and Methods of Use Thereof - Newly identified proteins as markers for the detection of breast, colon, lung and ovary tumors, or as therapeutic targets for their treatment, affinity ligands capable of selectively interacting with the newly identified markers and methods for tumor diagnosis and therapy using such ligands. | 05-30-2013 |
20150093396 | Prostate Tumor Markers And Methods Of Use Thereof - Newly identified proteins as markers for the detection of prostate tumors, or as targets for their therapeutic treatment, affinity ligands capable of selectively interacting with said markers as well as methods for tumor diagnosis and therapy using the same. | 04-02-2015 |
20160131656 | TUMOR MARKER, MONOCLONAL ANTIBODIES AND METHODS OF USE THEREOF - Newly identified proteins as markers for the detection of colon, ovary, kidney, esophagus and prostate tumors, or as therapeutic targets for their treatment; affinity ligands and particularly antibodies capable of selectively interacting with the tumor markers and methods for tumor diagnosis and thereapy using such antibodies. | 05-12-2016 |
Patent application number | Description | Published |
20090093444 | Cathepsin Cysteine Protease Inhibitors - This invention relates to a novel class of compounds which are cysteine protease inhibitors, including but not limited to, inhibitors of cathepsins K, L, S and B. These compounds are useful for treating diseases in which inhibition of bone resorption is indicated, such as osteoporosis. | 04-09-2009 |
20090170828 | Azetidine Derivatives as Inhibitors of Stearoyl-Coenzyme a Delta-9 Desaturase - Azetidine derivatives of structural formula I are selective inhibitors of stearoyl-coenzyme A delta-9 desaturase (SCD1) relative to other known stearoyl-coenzyme A desaturases. The compounds of the present invention are useful for the prevention and treatment of conditions related to abnormal lipid synthesis and metabolism, including cardiovascular disease; atherosclerosis; obesity; diabetes; neurological disease; metabolic syndrome; insulin resistance; liver steatosis; and non-alcoholic steatohepatitis. (I) | 07-02-2009 |
20090264479 | Papain Family Cysteine Protease Inhibitors for the Treatment of Parasitic Diseases - Several parasites responsible for mammalian diseases are dependent on cysteine protease for various life-cycle functions. Inhibition of these proteases can be useful in the treatment of these parasitic diseases, including toxoplasmosis, malaria, African trypanosomiasis, Chagas disease, leishmaniasis or schistosomiasis. | 10-22-2009 |
20090291988 | Reversible Inhibitors of Monoamine Oxidase A and B - The instant invention relates to compounds of formula I, diagrammed below, wherein R3, E, D and Y are defined in the application, which are useful as reversible inhibitors of monoamine oxidase-B and/or monoamine oxidase-A, and therefore useful to treat or prevent neurological diseases or conditions in mammals, preferably humans. | 11-26-2009 |
20100063013 | CATHEPSIN CYSTEINE PROTEASE INHIBITORS - The present invention relates to novel compounds of the formula (I), wherein R′-R7, X, Y, D and n are as defined in the specification. These compounds are cysteine protease inhibitors which include but are not limited to inhibitors of cathepsms K, L, S and B and are useful for treating diseases in which inhibition of bone resorption is indicated, such as osteoporosis. | 03-11-2010 |
Patent application number | Description | Published |
20130034879 | DNA Polymerases - A DNA polymerase mutant comprising a Taq DNA polymerase amino acid sequence with a mutation at one or more of the following selected amino acid positions: E189K, E230K, E507K, H28R, L30R, G38R, F73V, H75R, E76A, E76G, E76K, E90K, K206R, E315K, A348V, L351F, A439T, D452N, G504S, E507A, D551N, L552R, I553V, D578N, H676R, Q680R, D732G, E734G, E734K, F749V; wherein the polymerase mutant exhibits relative to wild-type DNA polymerase increased polymerase speed, increased affinity to DNA substrate and/or increased resistance to a DNA polymerase inhibitor; and wherein, when the mutation is E507K in combination with two or more further mutations or the mutation is Q680R in combination with four or more further mutations, at least one of the further mutations is at one of the selected amino acid positions; and when the mutation is I553V, this is not in combination with D551S. | 02-07-2013 |
20140011196 | RESTRICTION ENDONUCLEASES AND THEIR USES - A restriction endonuclease with a recognition sequence 5′-TCGA-3′. The restriction endonuclease is sensitive to the presence of a modified cytosine residue in the recognition sequence. Methods and kits using the restriction endonuclease with a recongition sequence 5′-TCGA-3′ are also disclosed. | 01-09-2014 |