Patent application number | Description | Published |
20090304044 | FREQUENCY-HOPPING ARRANGEMENT - A frequency-hopping arrangement comprises a basic-frequency branch (DIV | 12-10-2009 |
20110084741 | FAST-LOCKING BANG-BANG PLL WITH LOW OUPUT JITTER - The present invention relates to a gigitaol phaselocked loop DPLL ( | 04-14-2011 |
20110134964 | FREQUENCY SYNTHESIZER AND CONFIGURATION FOR AN ENHANCED FREQUENCY-HOPPING RATE - A frequency generating arrangement for generation of at least two predetermined frequencies is introduced. The arrangement comprises a phase locked loop circuit with at least two control value storage units and at least one controlled oscillator unit, wherein the control value storage units being configured to selectively output a control signal to the at least one voltage controlled oscillator unit, causing generation of one of the at least two predetermined frequencies. Frequency generating system for generation of ultra-fast hopping-frequency sequences comprises at least a first and a second frequency generating arrangement and further a controlling unit and a multiplexer unit for selectively connecting only one of the outputs of the two frequency generating arrangements with an output of the system. The controlling unit can be configured to control the system to generate a predetermined frequency sequence by controlling the two frequency generating arrangements such that during the period, in which one of the frequency generating arrangements is connected with the output of the system, the other frequency generating arrangement is controlled to lock to a next predetermined frequency of the predetermined frequency sequence, and to control the multiplexer unit pass the output of the other frequency generating arrangement to the system output after a predetermined time period; and repeating the controlling step in order to generate the predetermined frequency sequence. | 06-09-2011 |
20110140791 | ELECTRONIC CIRCUIT FREQUENCY GENERATION - An oscillation signal with a selectable frequency is generated with a phase locked loop ( | 06-16-2011 |
20110150043 | FREQUENCY HOPPING RECEIVER CIRCUIT - A frequency hopping receiver circuit has a frequency converter ( | 06-23-2011 |
20110188543 | STATE SAVING CONTROL FOR GENERATING AT LEAST ONE OUTPUT SIGNAL - The present invention proposes a control loop for receiving a reference signal r(t) and generating an output signal c(t) based on the reference signal r(t). The control loop comprises a subtracting element( | 08-04-2011 |
20120080529 | SMART CARD - The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part. | 04-05-2012 |
20120269304 | Symbol Clock Recovery Circuit - A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit. | 10-25-2012 |
20130064271 | ADAPTIVE EQUALIZER AND/OR ANTENNA TUNING - Equalization circuits and methods are implemented for a variety of applications. According to one such application, a transmitting device wirelessly communicates using an antenna. The device has a transmission circuit that is configured and arranged to transmit a first wireless signal using magnetic coupling between the antenna and a remote device, the coupling occurring over a wireless medium. A receiver circuit of the transmitting device is configured and arranged to receive a second wireless signal that is from the antenna and that represents the first wireless signal as modified by the coupling occurring over the wireless medium. An error circuit of the device is configured and arranged to generate an error signal by comparing the first wireless signal to the second wireless signal. An equalizer circuit of the device is configured and arranged to pre-code the first wireless signal with coding that compensates for inter-symbol interference by compensating for the error signal. | 03-14-2013 |
20140003484 | PRE-EQUALIZER FOR A DIGITALLY MODULATED RF SIGNAL AND METHOD | 01-02-2014 |
20140192934 | RECEIVER FILTER FOR DC-WANDER REMOVAL IN A CONTACTLESS SMARTCARD - Embodiments of a method for processing a baseband signal in a Direct Current (DC)-suppressed system, a system for processing a baseband signal in a DC-suppressed system, and a smart card are described. In one embodiment, a method for processing a baseband signal in a DC-suppressed system involves processing the baseband signal in the analog domain with a first high pass filter (HPF), converting the processed baseband signal to a digital signal, and processing the digital signal in the digital domain with a second HPF to provide a discrete-time differentiation of the baseband signal. Other embodiments are also described. | 07-10-2014 |
20150063517 | CLOCK SYNCHRONIZER FOR ALIGNING REMOTE DEVICES - Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal. | 03-05-2015 |