Patent application number | Description | Published |
20080242783 | POLYESTER COMPOSITIONS HAVING IMPROVED HEAT RESISTANCE - A composition of matter comprising a polyester composition derived from: (i) 20 to 80 mole percent of a first diol derived from a disubstituted xylene glycol of the formula (I): | 10-02-2008 |
20080242784 | POLYESTER COMPOSITIONS HAVING IMPROVED HEAT RESISTANCE - A composition of matter comprising a polyester composition derived from: (i) greater than 80 mole percent of a diol derived from a disubstituted xylene glycol of the formula (I): | 10-02-2008 |
20090275698 | Method of Making Polybutylene Terephthalate and Compositions and Articles Comprising the Same - A process for making modified polybutylene terephthalate random copolymers from a polyethylene terephthalate component includes reacting an oligomeric diol component selected from the group consisting of bis(hydroxybutyl)terephthalate, bis(hydroxybutyl)isophthalate, hydroxybutyl-hydroxyethyl terephthalate, and combinations thereof to a reactor; (i) a polyethylene terephthalate component selected from the group consisting of polyethylene terephthalate and polyethylene terephthalate copolymers with (ii) a diol component selected from the group consisting of 1,4-butanediol, ethylene glycol, propylene glycol, and combinations thereof, in the reactor under conditions sufficient to depolymerize the polyethylene terephthalate component into a first molten mixture; combining the first molten mixture is combined with 1,4-butanediol under conditions to form a second molten mixture; and placing the second molten mixture under conditions sufficient to produce the modified polybutylene terephthalate random copolymers. Also described are compositions and articles made from the process. | 11-05-2009 |
20110003964 | PROCESS FOR MAKING POLYBUTYLENE TEREPHTHALATE (PBT) FROM POLYETHYLENE TEREPHTHALATE (PET) - The invention relates to a process for making modified polybutylene terephththalate random copolymers from a polyethylene terephthalate component. The invention relates to a three step process in which a diol component selected from the group consisting of ethylene glycol, propylene glycol, and combinations thereof reacts with a polyethylene terephthalate component under conditions sufficient to depolymerize the polyethylene terephthalate component into a first molten mixture; and where the first molten mixture is combined with 1,4-butanediol under conditions that create a second molten mixture that is subsequently placed under subatmospheric conditions that produce the modified polybutylene terephthalate random copolymers. The invention also relates to compositions made from the process. | 01-06-2011 |
Patent application number | Description | Published |
20140032531 | SYSTEM AND METHOD FOR A SERVICE METERING FRAMEWORK IN A NETWORK ENVIRONMENT - A method is provided in one example embodiment and includes causing generation of a metered record associated with a metering event of an application executed within a cloud-based computing system, the metered record including a metering attribute and a corresponding value, the corresponding value being determined substantially simultaneous to a runtime execution of the application, and facilitating searching for the metered record based on the metering attribute and the corresponding value of the metering attribute. In specific embodiments, the metered record is communicated using a REpresentational State Transfer (REST) Application Programming Interface (API). In an example embodiment, the notification of the metering event can be received by any one of a REST API, a Java Messaging Service listener, an Extensible Messaging and Presence Protocol (XMPP) listener, or a metering plugin. | 01-30-2014 |
20150149628 | SYSTEM AND METHOD FOR A SERVICE METERING FRAMEWORK IN A NETWORK ENVIRONMENT - A method is provided in one example embodiment executed at a service metering framework (SMF) engine including a processor, and includes interfacing, by an event listener at the SMF engine, with an application being executed in a cloud by a remote client device, detecting a metering event associated with the application during execution of the application, receiving a value of at least one metering attribute associated with the metering event, and storing the at least one metering attribute and the value as a formatted metered record in a SMF database searchable according to the metering attribute. In a specific embodiment, the event listener exposes an application programming interface (API) of the SMF engine to the application to facilitate definitions of the metering event and the at least one metering attribute in the application. | 05-28-2015 |
20150254450 | DISPOSITION ENGINE FOR SINGLE SIGN ON (SSO) REQUESTS - Systems and methods are described for evaluating disposition of an SSO request. In one example, the method includes receiving the SSO request, the SSO request for accessing a secure service, the request having been denied authorization to access a first service, determining, based upon one or more criteria, where to direct the SSO request, and routing the SSO request to a second service, the routing based on the determining where to direct the SSO request. | 09-10-2015 |
20160094363 | VIRTUALIZED ON-DEMAND SERVICE DELIVERY BETWEEN DATA NETWORKS VIA SECURE EXCHANGE NETWORK - In one embodiment, a method comprises determining, by a network edge device in a first autonomous network, whether a second network edge device in a second autonomous network is authorized to submit a service request to the first autonomous network, the service request associated with one of providing or consuming an identified network-based service; identifying, by the network edge device within the first autonomous network, a third network edge device in a third autonomous network and identified as responsive to the service request for the identified network-based service; and sending instructions for establishing a secure communications between the second network edge device and the third network edge device via a data network distinct from the first, second, or third autonomous networks, for establishment of the identified network service between the second autonomous network and the third autonomous network via the data network. | 03-31-2016 |
Patent application number | Description | Published |
20110321017 | COMPUTER CODE DEBUGGING METHOD AND APPARATUS PROVIDING EXCEPTION BREAKPOINTS - A computer method and apparatus for debugging program code provides exception breakpoints with exception notification. Through a user interface, a user associates one or more exception breakpoints with respective different certain lines of code. A computer processor is configured to execute the subject program code in debug mode. During the executing, for each of the different certain lines of code, the processor: (a) pauses to pre-evaluate and determine tendency to throw an exception or spawn an interrupt, and (b) at the certain line of code, stops execution of the subject program code only if the pre-evaluating determined existence of a would-be exception or run-time interrupt. | 12-29-2011 |
20120102469 | DETERMINISTIC APPLICATION BREAKPOINT HALTING BY LOGICALLY RELATING BREAKPOINTS IN A GRAPH - An operating system or virtual machine of an information handling system (IHS) initializes a debugger tool for breakpoint management of an application during debugging operations. The operating system or virtual machine initializes a directed acyclic graph (DAG) tool that employs a graphical user interface (GUI) or command line interface (CLI) for breakpoint generation and manipulation. A programmer generates breakpoints and breakpoint conditions that support the debug of application software during design, development and test. The programmer constructs one or more DAGs for use by the debugger and DAG tool. The programmer initializes the application for debugging operations. When the debugger encounters a breakpoint, the DAG tool interprets the breakpoint. If the encountered breakpoint is part of any DAG, the DAG tool determines eligibility for the encountered breakpoint to either break or not break depending on the rules of the DAG construct. The programmer may modify and add new breakpoints during debug and runtime operations of the application. | 04-26-2012 |
20150067053 | MANAGING MESSAGE DISTRIBUTION IN A NETWORKED ENVIRONMENT - A method for managing message distribution in a networked computing environment. The method includes determining, for a particular topic, at least a first subscriber messaging engine and a second subscriber messaging engine to receive a topic message. The method includes determining that the first subscriber messaging engine is to act as a cache for the second subscriber messaging engine. The method includes sending the topic message to the first subscriber messaging engine. The method then includes sending a reference message to the second subscriber messaging engine, the reference message being able to be used to retrieve the topic message from the first subscriber messaging engine. | 03-05-2015 |
20150067071 | MANAGING MESSAGE DISTRIBUTION IN A NETWORKED ENVIRONMENT - A method for managing message distribution in a networked computing environment. The method includes determining, for a particular topic, at least a first subscriber messaging engine and a second subscriber messaging engine to receive a topic message. The method includes determining that the first subscriber messaging engine is to act as a cache for the second subscriber messaging engine. The method includes sending the topic message to the first subscriber messaging engine. The method then includes sending a reference message to the second subscriber messaging engine, the reference message being able to be used to retrieve the topic message from the first subscriber messaging engine. | 03-05-2015 |
20150149344 | SYNCHRONOUS SPLIT PAYMENT TRANSACTION MANAGEMENT - A software- and/or hardware-based transaction manager that reflects the application program interface(s) and/or system(s) for establishing sessions used to commit to, rollback and/or execute multiple payments made pursuant to a single financial transaction. This is accomplished by sharing sessions through co-browsing, or by continuous event logging and maintaining synchronous payments across a group of users in order to: support the lifecycle of each individual payment and session along with completion responsibility of the overall transaction. | 05-28-2015 |
20150149350 | SYNCHRONOUS SPLIT PAYMENT TRANSACTION MANAGEMENT - A software- and/or hardware-based transaction manager that reflects the application program interface(s) and/or system(s) for establishing sessions used to commit to, rollback and/or execute multiple payments made pursuant to a single financial transaction. This is accomplished by sharing sessions through co-browsing, or by continuous event logging and maintaining synchronous payments across a group of users in order to support the lifecycle of each individual payment and session along with completion responsibility of the overall transaction. | 05-28-2015 |
Patent application number | Description | Published |
20100218059 | On-Chip Seed Generation Using Boolean Functions for LFSR Re-Seeding Based Logic BIST Techniques for Low Cost Field Testability - This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip. | 08-26-2010 |
20110099442 | ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIONED SCAN CHAINS - A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can selectively control scan-in, scan-out and capture phases of scan tests for different scan chains of the IC to be independent. The number of pins required to interface the test controller with an external tester is less than the number of partitions that the test controller can support. According to another aspect, an IC includes a register corresponding to each partition to support transition fault (or LOS) testing. According to another aspect, an IC with partitioned scan chains includes serial to parallel and parallel to serial converters, thereby minimizing the external pins required to support scan tests. | 04-28-2011 |
20110225475 | LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR CHECKING AND CORRECTION FOR MEMORIES AND BUSES IN SYSTEM-ON-CHIPS, AND OTHER CIRCUITS, SYSTEMS AND PROCESSES - An electronic circuit ( | 09-15-2011 |
20120304031 | HYBRID TEST COMPRESSION ARCHITECTURE USING MULTIPLE CODECS FOR LOW PIN COUNT AND HIGH COMPRESSION DEVICES - This invention uses multiple codecs to efficiently achieve the right balance between compression and coverage for a given design. This application illustrates a simple example using two codecs including a high compression codec and a low compression codec. The test engineer generates a first set of test patterns using the high compression codec. If this high compression results in unacceptable fault coverage loss, the top-up patterns for additional coverage are generated using the low compression codec. The invention may use multiple codecs serially one after the other. The codecs can be of different types or parameters (such as compression ratio, debug tolerance and combinational codec versus sequential codec). | 11-29-2012 |
20130159800 | Scan Compression Architecture with Bypassable Scan Chains for Low Test Mode Power - This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations. | 06-20-2013 |
20130246889 | LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR CHECKING AND CORRECTION FOR MEMORIES AND BUSES IN SYSTEM-ON-CHIPS, AND OTHER CIRCUITS, SYSTEMS AND PROCESSES - An electronic circuit ( | 09-19-2013 |
20140208177 | CIRCUITS AND METHODS FOR DYNAMIC ALLOCATION OF SCAN TEST RESOURCES - A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports. | 07-24-2014 |
20150212152 | TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION - Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously. | 07-30-2015 |