Patent application number | Description | Published |
20130146982 | SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS - A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer. | 06-13-2013 |
20130146986 | SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS - A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor. | 06-13-2013 |
20130181289 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor. | 07-18-2013 |
20130275935 | PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS - An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase. | 10-17-2013 |
20130280905 | SOFTWARE AND METHOD FOR VIA SPACING IN A SEMICONDUCTOR DEVICE - A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance. | 10-24-2013 |
20130292772 | LAYOUT DESIGNS WITH VIA ROUTING STRUCTURES - An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure. | 11-07-2013 |
20130292773 | CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES - An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a gate cut region across the first gate structure, the second gate structure, or a combination thereof; providing a first gate contact over the first gate structure; providing a second gate contact over the second gate structure; and providing a diffusion contact structure coupling the first gate contact to the second gate contact, the diffusion contact structure having vertices within the gate cut region. | 11-07-2013 |
20140001563 | SEMICONDUCTOR DEVICES FORMED ON A CONTINUOUS ACTIVE REGION WITH AN ISOLATING CONDUCTIVE STRUCTURE POSITIONED BETWEEN SUCH SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME | 01-02-2014 |
20140027918 | CROSS-COUPLING BASED DESIGN USING DIFFUSION CONTACT STRUCTURES - An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact. | 01-30-2014 |
20140035151 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DOUBLE PATTERNING PROCESSES - Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns. | 02-06-2014 |
20140042641 | MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES - An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions. | 02-13-2014 |
Patent application number | Description | Published |
20140077380 | BIT CELL WITH DOUBLE PATTERNED METAL LAYER STRUCTURES - An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge. | 03-20-2014 |
20140097892 | DOUBLE PATTERNING COMPATIBLE COLORLESS M1 ROUTE - A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone. | 04-10-2014 |
20140131816 | CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES - An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a gate cut region across the first gate structure, the second gate structure, or a combination thereof; providing a first gate contact over the first gate structure; providing a second gate contact over the second gate structure; and providing a diffusion contact structure coupling the first gate contact to the second gate contact, the diffusion contact structure having vertices within the gate cut region. | 05-15-2014 |
20140183638 | METHODS OF USING A TRENCH SALICIDE ROUTING LAYER - Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure. | 07-03-2014 |
20140258960 | INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESIGN LAYOUTS - An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system. | 09-11-2014 |
20140282323 | PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN - A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions. | 09-18-2014 |
20140327146 | METHODS FOR IMPROVING DOUBLE PATTERNING ROUTE EFFICIENCY - A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs. | 11-06-2014 |
20140327153 | STANDARD CELL CONNECTION FOR CIRCUIT ROUTING - Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M | 11-06-2014 |
20140332967 | BIT CELL WITH DOUBLE PATTERENED METAL LAYER STRUCTURES - An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge. | 11-13-2014 |
20140339610 | FINFET DEVICE AND METHOD OF FABRICATION - Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency. | 11-20-2014 |
20140339647 | DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND METHODS OF MAKING SAME - One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively | 11-20-2014 |
20140346662 | FORMING MODIFIED CELL ARCHITECTURE FOR FINFET TECHNOLOGY AND RESULTING DEVICE - Methods for accommodating a non-integer multiple of the M2 pitch for the cell height of a semiconductor cell and the resulting devices are disclosed. Embodiments may include forming a cell within an integrated circuit (IC) with a height of a first integer and a remainder times a track pitch of a metal track layer, and forming power rails within the metal track layer at boundaries of the cell accommodating for the remainder. | 11-27-2014 |
20140353842 | WIDE PIN FOR IMPROVED CIRCUIT ROUTING - Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size. | 12-04-2014 |
20150052494 | POWER RAIL LAYOUT FOR DENSE STANDARD CELL LIBRARY - A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area. | 02-19-2015 |
Patent application number | Description | Published |
20090021989 | PROGRAMMABLE BIAS FOR A MEMORY ARRAY - A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values. | 01-22-2009 |
20090031163 | SPEEDPATH REPAIR IN AN INTEGRATED CIRCUIT - A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also comprises a second plurality of transistors of a second channel length having an expected equivalent functionality as the first plurality of transistors and disposed in parallel with the first plurality of transistors along the speedpath, wherein the second channel length is different from the first channel length. In addition, the circuit comprises an element configured to selectively replace the first plurality of transistors with the second plurality of transistors in response to a determination that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath. In one embodiment, the second channel length is a sub-minimal geometry with respect to the first channel length. | 01-29-2009 |
20090242994 | HYBRID TRANSISTOR BASED POWER GATING SWITCH CIRCUIT AND METHOD - A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode. | 10-01-2009 |