Patent application number | Description | Published |
20080269474 | Novel shRNA molecules and methods of use thereof - The present invention relates to certain novel shRNA molecules and methods of use thereof. According to certain embodiments of the present invention, methods for reducing the expression level of a target gene are provided. Such methods generally comprise providing a cell with one or more precursor nucleic acid sequences that encode two or more RNA molecules. A first RNA molecule comprises a double stranded sequence, which includes a guide strand sequence that is complementary to a portion of an mRNA transcript encoded by the target gene. In addition, a second RNA molecule comprises a second double stranded sequence, which includes a second guide strand sequence that is partially complementary to a portion of the mRNA transcript encoded by the target gene. Preferably, the second guide strand sequence comprises one or more bases that are mismatched with a nucleic acid sequence of the mRNA transcript encoded by the target gene. | 10-30-2008 |
20100166845 | INDIVIDUALIZED CANCER THERAPY - In certain embodiments, the invention provides methods for treating cancer, comprising: (a) obtaining a specimen of cancer tissue and normal tissue from a patient; (b) extracting total protein and RNA from the cancer tissue and normal tissue; (c) obtaining a protein expression profile of the cancer tissue and normal tissue; (d) identifying over-expressed proteins in the cancer tissue; (e) comparing the protein expression profile to a gene expression profile; (f) identifying at least one prioritized protein target by assessing connectivity of each said over-expressed protein to other cancer-related or stimulatory proteins; (g) designing a first RNA interference expression cassette to modulate the expression of at least one gene encoding the prioritized target protein; (h): designing a first RNA interference expression cassette to modulate the expression of at least one gene encoding a protein of higher priority in the signaling pathway in which the first protein is a component; (i) incorporating the first cassette into a first delivery vehicle; (j) providing a patient with an effective amount of the first delivery vehicle; (k) extracting total protein and RNA from the treated cancer tissue; (l) identifying over-expressed proteins in the treated cancer tissue; (m) designing a second RNA interference expression cassette to modulate the expression of a second prioritized protein in the treated tissue; (n) incorporating the second cassette into a second delivery vehicle; (o) providing the previously treated patient with an effective amount of the second delivery vehicle; (p) identifying a novel protein signal following prior treatment with protein specific knockdown; (q) identifying a gene mutation provided by gene sequencing/microarray on assessment of other protein signals; and (r) identifying of a novel protein signal as a result of determination of the gene mutation and assessment of other protein signals to, directly or indirectly, modify the expression (i.e., production) of such proteins. | 07-01-2010 |
20110117183 | Novel Therapeutic RNA Interference Technology Targeted to the PDX-1 Oncogene in PDX-1 Expressing Neuroendocrine Tumors - A bifunctional shRNA-based composition and methods for knocking down the expression of the PDX-1 oncogene in target cells is described herein. The invention also provides methods to deliver the shRNA-containing expression vectors to target tissues overexpressing the PDX-1 oncogene. | 05-19-2011 |
20110150832 | FURIN-KNOCKDOWN BI-FUNCTIONAL RNA - Compositions and methods to attenuate the immunosuppressive activity of TGF-β through the use of bi-functional shRNAs is described herein. The bi-functional shRNAs of the present invention knocks down the expression of furin in cancer cells to augment tumor antigen expression, presentation, and processing through expression of the GM-CSF transgene. | 06-23-2011 |
20110262408 | FURIN-KNOCKDOWN AND GM-CSF-AUGMENTED (FANG) CANCER VACCINE - Compositions and methods for cancer treatment are discloses herein. More specifically the present invention describes an autologous cancer vaccine genetically modified for Furin knockdown and GM-CSF expression. The vaccine described herein attenuates the immunosuppressive activity of TGF-β through the use of bi-functional shRNAs to knock down the expression of furin in cancer cells, and to augment tumor antigen expression, presentation, and processing through expression of the GM-CSF transgene. | 10-27-2011 |
20110286979 | CHEMOSENSITIZATION BY BI-FUNCTIONAL SMALL HAIRPIN RNA (bi-shRNA) - Compositions and methods of augmenting the anti-tumor activities of docetaxel and other taxanes by combination with a bi-functional small hairpin RNA (bi-shRNA) is described herein. The instant invention describes the interactive outcome of STMN1 knockdown with docetaxel. In vitro docetaxel (DOC) dose response assessments with or without co-treatment with bi-shRNA | 11-24-2011 |
20120183955 | Design and construction of Bifunctional Short Hairpin RNA - A method for designing a bi-shRNA expression cassette encoding a bi-shRNA comprising: selecting one or more target site sequences; providing a backbone sequence comprising a first and a second stem-loop structure, inserting a first passenger strand and a second passenger strand and providing for synthesis of the bi-shRNA expression cassette. | 07-19-2012 |
20120251617 | BI-FUNCTIONAL SHRNA TARGETING STATHMIN 1 AND USES THEREOF - The present invention includes bifunctional shRNAs capable of reducing an expression of a Stathmin 1 gene; wherein at least one target site sequence of the bifunctional RNA molecule is located within the Stathmin 1 gene, wherein the bifunctional RNA molecule is capable of activating a cleavage-dependent and a cleavage-independent RNA-induced silencing complex for reducing the expression level of Stathmin 1. | 10-04-2012 |
20130064881 | COMPOSITIONS AND METHODS FOR TREATING PROSTATE CANCER - Compositions and methods to interfere with Androgen Receptor (AR) action based on bifunctional shRNA, targeting the AR and/or expression of SRC derived peptides are disclosed herein. | 03-14-2013 |
20130071928 | NOVEL SHRNA MOLECULES AND METHODS OF USE THEREOF - The present invention relates to certain novel shRNA molecules and methods of use thereof. According to certain embodiments of the present invention, methods for reducing the expression level of a target gene are provided. Such methods generally comprise providing a cell with one or more precursor nucleic acid sequences that encode two or more RNA molecules. A first RNA molecule comprises a double stranded sequence, which includes a guide strand sequence that is complementary to a portion of an mRNA transcript encoded by the target gene. In addition, a second RNA molecule comprises a second double stranded sequence, which includes a second guide strand sequence that is partially complementary to a portion of the mRNA transcript encoded by the target gene. Preferably, the second guide strand sequence comprises one or more bases that are mismatched with a nucleic acid sequence of the mRNA transcript encoded by the target gene. | 03-21-2013 |
20130078279 | FURIN-KNOCKDOWN AND GM-CSF-AUGMENTED (FANG) CANCER VACCINE - Compositions and methods for cancer treatment are discloses herein. More specifically the present invention describes an autologous cancer vaccine genetically modified for Furin knockdown and GM-CSF expression. The vaccine described herein attenuates the immunosuppressive activity of TGF-β through the use of bi-functional shRNAs to knock down the expression of furin in cancer cells, and to augment tumor antigen expression, presentation, and processing through expression of the GM-CSF transgene. | 03-28-2013 |
20130078719 | NOVEL SHRNA MOLECULES AND METHODS OF USE THEREOF - The present invention relates to certain novel shRNA molecules and methods of use thereof. According to certain embodiments of the present invention, methods for reducing the expression level of a target gene are provided. Such methods generally comprise providing a cell with one or more precursor nucleic acid sequences that encode two or more RNA molecules. A first RNA molecule comprises a double stranded sequence, which includes a guide strand sequence that is complementary to a portion of an mRNA transcript encoded by the target gene. In addition, a second RNA molecule comprises a second double stranded sequence, which includes a second guide strand sequence that is partially complementary to a portion of the mRNA transcript encoded by the target gene. Preferably, the second guide strand sequence comprises one or more bases that are mismatched with a nucleic acid sequence of the mRNA transcript encoded by the target gene. | 03-28-2013 |
20130084331 | Novel Therapeutic RNA Interference Technology Targeted to the PDX-1 Oncogene in PDX-1 Expressing Neuroendocrine Tumors - A bifunctional shRNA-based composition and methods for knocking down the expression of the PDX-1 oncogene in target cells is described herein. The invention also provides methods to deliver the shRNA-containing expression vectors to target tissues overexpressing the PDX-1 oncogene. | 04-04-2013 |
20130259925 | METHODS AND COMPOSITIONS TO TREAT CANCER USING BIFUNCTIONAL SRC 3 shRNA - The present invention includes compositions and methods of making and using an expression vector comprising a promoter and a nucleic acid insert operably linked to the promoter, wherein the insert encodes one or more short hairpin RNAs (shRNA) capable of inhibiting an expression of a SRC-3 gene via RNA interference, wherein the one or more shRNA comprise a bifunctional RNA molecule that activates a cleavage-dependent and a cleavage-independent RNA-induced silencing complex for reducing the expression level of the SRC-3. | 10-03-2013 |
20130259926 | BI-FUNCTIONAL shRNA TARGETING MESOTHELIN AND USES THEREOF - The present invention includes bifunctional shRNAs capable of reducing an expression of a Mesothelin gene; wherein at least one target site sequence of the bifunctional RNA molecule is located within the Mesothelin, wherein the bifunctional RNA molecule is capable of activating a cleavage-dependent and a cleavage-independent RNA-induced silencing complex for reducing the expression level of Mesothelin. | 10-03-2013 |
20130259927 | Ewing's Sarcoma Bifunctional shRNA Design - The present invention includes compositions and methods of making and using an imaging label comprising an expression vector comprising a promoter; and a nucleic acid insert operably linked to the promoter, wherein the insert encodes one or more short hairpin RNAs (shRNA) capable of inhibiting an expression of a target gene sequence that is a EWS-FLI1 fusion gene, a EWSR1-ERG fusion gene, or both in Ewing's sarcoma via RNA interference; wherein the one or more shRNA comprise a bifunctional RNA molecule that activates a cleavage-dependent and a cleavage-independent RNA-induced silencing complex for reducing the expression level of the target gene. | 10-03-2013 |
20130266639 | METHODS FOR TREATING TRIPLE NEGATIVE BREAST CANCER USING BIFUNCTIONAL SRC 3 shRNA - The present invention includes compositions and methods treating triple negative breast cancer comprising administering a therapeutically effective amount of a formulation that includes vector that expresses an SRC-1-specific bifunctional shRNA, an SRC-3-specific bifunctional shRNA, or both, to impair triple negative breast cancer cell growth. | 10-10-2013 |
20130295160 | ANTAGONISTS OF MIR-196A - A miR-196a antagonist capable of inhibiting a miR-196a activity, the miR-196a antagonist comprising one or more target sites for miR-196a. Included is also an expression vector comprising a promoter and a nucleic acid insert operably linked to the promoter, wherein the insert encodes one or more miR-196a antagonists capable of inhibiting a miR-196a activity. In one example, the one or more miR-196a antagonists comprise at least one stem-loop structure comprising a guide strand that comprises a sequence that is complementary to miR-196a, the stem-loop structure further comprising a passenger strand that comprises a mismatch. | 11-07-2013 |
20130302407 | Bi-Functional Short-Hairpin RNA (Bi-shRNA) Specific for Single-Nucleotide KRAS Mutations - The present invention includes compositions and methods for making and using a bifunctional shRNAs capable of reducing an expression of a K-ras gene, e.g., a mutated K-ras gene, wherein at least one target site sequence of the bifunctional RNA molecule is located within the K-ras gene and wherein the bifunctional RNA molecule is capable of activating a cleavage-dependent and a cleavage-independent RNA-induced silencing complex for reducing the expression level of K-ras. | 11-14-2013 |
20140134236 | INDIVIDUALIZED CANCER THERAPY - In certain preferred embodiments, the invention provides methods for treating cancer, which comprise (a) obtaining a specimen of cancer tissue from a patient; (b) obtaining a specimen of normal tissue in the proximity of the cancer tissue from such patient; (c) extracting total protein and RNA from the cancer tissue and normal tissue; (d) obtaining a protein expression profile of the cancer tissue and normal tissue using 2D DIGE and mass spectrometry; (e) identifying proteins that are expressed in such cancer tissue at significantly different levels than in the normal tissue; (f) obtaining a gene expression profile of the cancer tissue and normal tissue using microarray technology and comparing the results thereof to the protein expression profile; (g) prioritizing over-expressed proteins by assessing the connectivity thereof to other cancer-related or stimulatory proteins; (h) designing an appropriate RNA interference expression cassette to, directly or indirectly, modulate the expression of genes encoding such prioritized proteins; (i) incorporating said cassette into an appropriate delivery vehicle; and (j) providing the patient with an effective amount of the delivery vehicle to, directly or indirectly, modify the expression (i.e., production) of such proteins. | 05-15-2014 |
20140242639 | CONSTRUCTION OF BIFUNCTIONAL SHORT HAIRPIN RNA - A method for designing a bi-shRNA expression cassette encoding a bi-shRNA comprising: selecting one or more target site sequences; providing a backbone sequence comprising a first and a second stem-loop structure, inserting a first passenger strand and a second passenger strand and providing for synthesis of the bi-shRNA expression cassette. | 08-28-2014 |
20150086619 | INDIVIDUALIZED CANCER THERAPY - In certain embodiments, the invention provides methods for treating cancer, comprising: obtaining a specimen of cancer tissue and normal tissue from a patient; extracting total protein; obtaining a protein expression profile; identifying over-expressed proteins; comparing the protein expression profile to a gene expression profile; identifying at least one prioritized protein target; designing a first RNA interference expression cassette; designing a first RNA interference expression cassette to modulate the expression of at least one gene encoding; incorporating the first cassette into a delivery vehicle; and providing a patient with an effective amount of the first delivery vehicle. | 03-26-2015 |
Patent application number | Description | Published |
20080288785 | Data Security and Digital Rights Management System - A system and method is described for enhancing data security in a broad range of electronic systems through encryption and decryption of addresses in physical memory to which data is written and from which data is read. It can be implemented through software, hardware, firmware or any combination thereof. Implementation in Digital Rights Management execution using the invention reduces cost, enhances performance, and provides additional transactional security. | 11-20-2008 |
20110060870 | NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES - A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system. | 03-10-2011 |
20110110157 | RANDOM ACCESS MEMORY WITH CMOS-COMPATIBLE NONVOLATILE STORAGE ELEMENT AND PARALLEL STORAGE CAPACITOR - Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element. | 05-12-2011 |
20120226934 | MISSION CRITICAL NAND FLASH - A flash controller reliably stores data in NAND FLASH by encoding data using an encoding algorithm, and storing that data across multiple pages of the memory. In one embodiment, true data is accepted by the controller, and the controller in turn creates coded data that is the bit-for-bit complement of the true data. The true data and the coded data are then written to the NAND FLASH on a page by page basis. A property of the coding techniques used is that, in at least some cases, detected errors can be corrected. | 09-06-2012 |
20120239863 | NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES - A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system. | 09-20-2012 |
20120262980 | RANDOM ACCESS MEMORY WITH CMOS-COMPATIBLE NONVOLATILE STORAGE ELEMENT AND PARALLEL STORAGE CAPACITOR - Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element. | 10-18-2012 |
20130021846 | LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM - A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module. | 01-24-2013 |
Patent application number | Description | Published |
20100153137 | MULTIDIMENSIONAL INSURANCE QUOTING SYSTEM AND METHOD - A system, method and computer program product for providing insurance rate quotes comprises a quotation module executable by a processor, the quotation module configured to receive a set of parameter values from a user. The quotation module is also configured to transmit the set of parameter values to least one insurance provider and obtain a rate quote based on the set of parameter values. The quotation module is further configured to vary, transparently to the user, at least one value of the set of parameter values and obtain at least one additional rate quote from the insurance provider based on the varied set of parameter values. | 06-17-2010 |
20100324944 | INSURANCE CODE QUOTE RESOLUTION SYSTEM AND METHOD - An insurance code resolution system comprises a quotation module executable by a processor. The quotation module is configured to generate a quote request and submit the quote request to at least one insurance provider where the quote request comprises at least one code representing a parameter value for the quote. The quotation module is also configured to receive a response from the insurance provider associated with the quote request and, if the response indicates an inconsistency related to the at least one code, automatically initiate an action to modify the at least one code. | 12-23-2010 |
20110022417 | INSURANCE QUOTING SYSTEM AND METHOD - An insurance quoting system comprises a quotation module executable by a processor where the quotation module is configured to receive from a user a request for a rate quote for an insurance product via a website associated with a first broker. The quotation module is also configured to determine whether the first broker is authorized to provide the insurance product to the user and, if the first broker is not authorized to provide the insurance product, automatically locate a second broker authorized to provide the insurance product to the user. | 01-27-2011 |
20120246702 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR ACCESS AUTHENTICATION - According to one aspect of the present disclosure, a method and technique for access authentication is disclosed. The method includes: responsive to receiving an access request from a user for a secure resource, logging an Internet Protocol (IP) address of the access request; transmitting a uniform resource locator (URL) to the user via an electronic mail message; responsive to receiving a request for the URL, logging an IP address corresponding to the URL request; and responsive to validating the IP address corresponding to the URL request with the IP address of the access request, providing access to the secure resource. | 09-27-2012 |
20130024215 | INSURANCE QUOTING APPLICATION FOR HANDHELD DEVICE - A method, system and computer program product for providing location-based insurance rate quotes. The method and technique includes prompting, by a mobile electronic device, a user of the mobile electronic device to input a name into the mobile electronic device to associate with a request for an insurance rate quote; transmitting, by the mobile electronic device over a network to a server, the request for the insurance rate quote, the request including the name and location data corresponding to a location of the mobile electronic device; receiving from the server by the mobile electronic device an indication of an insurable property based on the location data; and receiving and displaying on the mobile electronic device a response received from the server including the insurance rate quote for the insurable property. | 01-24-2013 |
20130090950 | POLICY EVENT MANAGEMENT SYSTEM AND METHOD - According to one aspect of the present disclosure, a method and technique for policy event management is disclosed. The method includes: receiving by a broker an electronic communication from an insurance provider of an event related to a policy of a consumer serviced by the insurance provider; responsive to receiving the notice, automatically determining whether the event meets at least one event criteria monitored by the broker; and responsive to determining that the event corresponds to at least one event criteria monitored by the broker, automatically initiating an action related to the event. | 04-11-2013 |
20130110554 | POLICY MANAGEMENT SYSTEM AND METHOD | 05-02-2013 |
Patent application number | Description | Published |
20150084975 | LOAD/STORE OPERATIONS IN TEXTURE HARDWARE - Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption. | 03-26-2015 |
20150097847 | MANAGING MEMORY REGIONS TO SUPPORT SPARSE MAPPINGS - One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management. | 04-09-2015 |
20150097851 | APPROACH TO CACHING DECODED TEXTURE DATA WITH VARIABLE DIMENSIONS - A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map. | 04-09-2015 |
Patent application number | Description | Published |
20090213946 | PARTIAL RECONFIGURATION FOR A MIMO-OFDM COMMUNICATION SYSTEM - Partial reconfiguration of programmable logic for supporting a Multiple-input, Multiple-Output Orthogonal Frequency Division Multiplexing (“MIMO-OFDM”) communication system is described. A PHY block in a programmable device may be instantiated generally in part in programmable logic of the programmable device. Control information is obtained for a network node when deployed and/or from a wireless transmission of a packet or frame, which is demodulated in the PHY block. Responsive to the control information demodulated, bitstream information is obtained to configure the portion of the PHY block using the programmable logic of the programmable device. | 08-27-2009 |
20090213947 | BLOCK BOUNDARY DETECTION FOR A WIRELESS COMMUNICATION SYSTEM - Method and apparatus for block boundary detection is described. A signal is received. The signal is quantized to provide a quantized signal to at least one correlator, the quantized signal being a sequence of samples. The sequence of samples and a reference template including totaling partial results from the at least one correlator are cross-correlated to provide a result, the result being a symbol timing synchronization responsive to the cross-correlation also known as block boundary detection. The cross-correlation is provided in part by combining by exclusive-ORing a regression vector obtained from the sequence of samples and a coefficient term vector obtained from the reference template. | 08-27-2009 |
20100272195 | PEAK-TO-AVERAGE POWER RATIO REDUCTION WITH BOUNDED ERROR VECTOR MAGNITUDE - Method and apparatus for signal processing to minimize the peak to average power ratio of an Orthogonal Frequency Division Multiplexing (“OFDM”) or Orthogonal Frequency Division Multiple Access (“OFDMA”) signal with bounded error vector magnitude for an integrated circuit are described. An Active Constellation Extension (“ACE”) iteration, using a constellation points adjustment module, is performed. Symbols outside of a bounded region after the ACE iteration are identified. The bounded region is determined responsive to an error vector magnitude target. The symbols identified are translated to the bounded region. | 10-28-2010 |
20110125819 | MINIMUM MEAN SQUARE ERROR PROCESSING - A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication. | 05-26-2011 |
20130138712 | MINIMUM MEAN SQUARE ERROR PROCESSING - A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication. | 05-30-2013 |
20130144926 | MINIMUM MEAN SQUARE ERROR PROCESSING - A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication. | 06-06-2013 |
20130151911 | REDUCTION IN DECODER LOOP ITERATIONS - An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information. | 06-13-2013 |
Patent application number | Description | Published |
20120081141 | On-Chip Delay Measurement Through a Transistor Array - Methods and apparatus are provided for measuring a delay through one or more transistors in an array of transistors. The delay through one or more transistors in an array of transistors is measured by selecting one of the transistors in the array; and applying a clock signal to the selected transistor, wherein an output of the selected transistor is applied to a first input of a logic gate having at least two inputs and wherein a second clock signal based on the clock signal is applied to a second input of the logic gate, and wherein an output of the logic gate indicates a difference in arrival times of the signals at the two inputs. In one variation, a clock signal is applied to the selected transistor and a variable delay circuit; and an output of the selected transistor is applied to a data input of a latch having a clock input and a data input while an output of the variable delay circuit is applied to a clock input of the latch. The delay applied by the variable delay circuit to the clock signal is adjusted until a predefined transition is detected in an output of the latch. If the delay is measured through a plurality of transistors in the array, the delay variation among the plurality of transistors can be obtained. | 04-05-2012 |
20120182079 | MONITORING NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) AND/OR POSITIVE BIAS TEMPERATURE INSTABILITY (PBTI) - A ring oscillator circuit for measurement of negative bias temperature instability effect and/or positive bias temperature instability effect includes a ring oscillator having first and second rails, and an odd number (at least 3) of repeating circuit structures. Each of the repeating circuit structures in turn includes an input terminal and an output terminal; a first p-type transistor having a gate, a first drain-source terminal coupled to the first rail, and a second drain source terminal selectively coupled to the output terminal; a first n-type transistor having a gate, a first drain-source terminal coupled to the second rail, and a second drain source terminal selectively coupled to the output terminal; and repeating-circuit-structure control circuitry. The ring oscillator circuit also includes a voltage supply and control block. | 07-19-2012 |
20120320689 | Performing Logic Functions on More Than One Memory Cell Within an Array of Memory Cells - A circuit structure is provided for performing a logic function within a memory. A plurality of read word line transistors are provided that receive a read word line signal and, upon receiving the read word line signal, the plurality of read word line transistors provide a path from a plurality of bit-line transistors associated with a plurality of physically adjacent memory cells to a read bit-line. In response to an associated memory cell within the memory storing a first value, each of the plurality of read bit-line transistors turns on and provides a path to ground thereby causing a first output value to be output on the read bit-line. In response to all of the plurality of memory cells storing a second value, the plurality of read bit-line transistors turn off thereby preventing a path to ground and a second output value is output on the read bit-line. | 12-20-2012 |
20130138403 | USAGE-BASED TEMPORAL DEGRADATION ESTIMATION FOR MEMORY ELEMENTS - Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model. | 05-30-2013 |
20130138407 | USAGE-BASED TEMPORAL DEGRADATION ESTIMATION FOR MEMORY ELEMENTS - Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model. | 05-30-2013 |
20130253868 | ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS - A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. Performing a timing analysis using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis being static or statistical. | 09-26-2013 |
20130254731 | ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS - A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. A timing analysis is performed using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis is static or statistical. | 09-26-2013 |
20130258750 | DUAL-CELL MTJ STRUCTURE WITH INDIVIDUAL ACCESS AND LOGICAL COMBINATION ABILITY - A dual-cell spin-transfer torque random-access memory including a first magnetic tunneling junction and a second magnetic tunneling junction. An access circuit is coupled to the first and second magnetic tunneling junctions such that independent read and write access is provided to bits stored in the first and second magnetic tunneling junctions. | 10-03-2013 |
20150154331 | ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS - A system for estimating delay deterioration in an integrated circuit includes a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit. A netlist generator generates an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations. A timing analyzer performs a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes. | 06-04-2015 |
Patent application number | Description | Published |
20090287776 | SYSTEM AND METHOD FOR AUTOGENERATED EMAIL FOLLOW-UP - A system and method for transmitting an electronic mail message to one or more intended recipients, which allows the user to designate that an electronic mail message contains a request for information which requires a reply from the one or more intended recipients, monitors electronic mail messages incoming to the sender to detect whether a reply has been received within the response period, and upon receiving a reply from any of the one or more intended recipients, presents the reply to the sender with one or more user-selectable icons which allow the sender to accept the reply as sufficient or request more information from the one or more intended recipients in response to selection of a user-selectable icon. | 11-19-2009 |
20100241767 | Migrating Domains from One Physical Data Processing System to Another - A system and method for migrating domains from one physical data processing system to another are provided. With the system and method, domains may be assigned direct access to physical I/O devices but in the case of migration, the I/O devices may be converted to virtual I/O devices without service interruption. At this point, the domain may be migrated without limitation. Upon completion of the migration process, the domain may be converted back to using direct physical access, if available in the new data processing system to which the domain is migrated. Alternatively, the virtualized access to the I/O devices may continue to be used until the domain is migrated back to the original data processing system. Once migration back to the original data processing system is completed, the access may be converted back to direct access with the original physical I/O devices. | 09-23-2010 |
20100250786 | Migrating Domains from One Physical Data Processing System to Another - A system and method for migrating domains from one physical data processing system to another are provided. With the system and method, domains may be assigned direct access to physical I/O devices but in the case of migration, the I/O devices may be converted to virtual I/O devices without service interruption. At this point, the domain may be migrated without limitation. Upon completion of the migration process, the domain may be converted back to using direct physical access, if available in the new data processing system to which the domain is migrated. Alternatively, the virtualized access to the I/O devices may continue to be used until the domain is migrated back to the original data processing system. Once migration back to the original data processing system is completed, the access may be converted back to direct access with the original physical I/O devices. | 09-30-2010 |
Patent application number | Description | Published |
20120004544 | DELIVERY OF BIOLOGICAL COMPOUNDS TO ISCHEMIC AND/OR INFARCTED TISSUE - The delivery of biological compounds to ischemic and/or infarcted tissue are described herein where such a system may include a deployment catheter and an attached imaging hood deployable into an expanded configuration. In use, the imaging hood is placed against or adjacent to a region of tissue to be imaged in a body lumen that is normally filled with an opaque bodily fluid such as blood. A translucent or transparent fluid, such as saline, can be pumped into the imaging hood until the fluid displaces any blood, thereby leaving a clear region of tissue to be imaged via an imaging element in the deployment catheter. Additionally, any number of therapeutic tools can also be passed through the deployment catheter and into the imaging hood for performing any number of procedures on the tissue for identifying, locating, and/or accessing ischemic and/or infarcted tissue. | 01-05-2012 |
20120226166 | DELIVERY OF BIOLOGICAL COMPOUNDS TO ISCHEMIC AND/OR INFARCTED TISSUE - The delivery of biological compounds to ischemic and/or infarcted tissue are described herein where such a system may include a deployment catheter and an attached imaging hood deployable into an expanded configuration. In use, the imaging hood is placed against or adjacent to a region of tissue to be imaged in a body lumen that is normally filled with an opaque bodily fluid such as blood. A translucent or transparent fluid, such as saline, can be pumped into the imaging hood until the fluid displaces any blood, thereby leaving a clear region of tissue to be imaged via an imaging element in the deployment catheter. Additionally, any number of therapeutic tools can also be passed through the deployment catheter and into the imaging hood for performing any number of procedures on the tissue for identifying, locating, and/or accessing ischemic and/or infarcted tissue. | 09-06-2012 |
20140350412 | Delivery Of Biological Compounds To Ischemic And/Or Infarcted Tissue - The delivery of biological compounds to ischemic and/or infarcted tissue are described herein where such a system may include a deployment catheter and an attached imaging hood deployable into an expanded configuration. In use, the imaging hood is placed against or adjacent to a region of tissue to be imaged in a body lumen that is normally filled with an opaque bodily fluid such as blood. A translucent or transparent fluid, such as saline, can be pumped into the imaging hood until the fluid displaces any blood, thereby leaving a clear region of tissue to be imaged via an imaging element in the deployment catheter. Additionally, any number of therapeutic tools can also be passed through the deployment catheter and into the imaging hood for performing any number of procedures on the tissue for identifying, locating, and/or accessing ischemic and/or infarcted tissue. | 11-27-2014 |
Patent application number | Description | Published |
20080241332 | Process for Producing Nut-Based Expandable Pellets and Nut-Based Snack Chips - A method is disclosed for producing an intermediary product in the form of a nut-based pellet that is capable of being stored for up to about six months. To form the nut pellets, a nut dough is passed through an extruder. The extrudate produced is then cut into pellets and dried. Starch pellets can then optionally be mixed with the nut pellets or small nut pieces and cooked to form a snack chip. The snack chip is formed by compressing and cooking the pellet mixture, expanding the pellet mixture, and compressing the pellet mixture again. | 10-02-2008 |
20080248179 | DIRECT EXPANDED SNACK MADE WITH PEANUT FLOUR AND METHOD FOR MAKING - A method for making a direct expanded snack piece shaped like a peanut is disclosed. Ingredients comprising peanut flour, ground corn product, rice flour and oat flour are introduced into an extruder. The ingredients are hydrated and extruded through an orifice adapted to produce a puffed snack piece shaped like a peanut and cut into puffed snacks. The puffed snacks are dried and seasoned. | 10-09-2008 |
20080279994 | METHOD FOR REDUCING ACRYLAMIDE FORMATION IN THERMALLY PROCESSED FOODS - A method for reducing the amount of acrylamide in thermally processed foods. This invention permits the production of foods having significantly reduced levels of acrylamide. The method relies on the manipulation of various unit operations used in the production of food products, particularly the peeling, cooking, and rejecting unit operations. For example, the peeling unit operation can be modified to provide a more fully peeled potato slice. The cooking unit operation can be modified by cooking to higher moisture and/or at lower hot oil temperatures to minimize the high-temperature/low-moisture conditions most favorable for acrylamide formation. The rejection unit operation can be modified to reject defects that result in high levels of acrylamide. | 11-13-2008 |
20090191313 | Method for Making a Coated Food Product Having a Heat Susceptible Coating - A method for making a coated food product having a heat susceptible coating is disclosed. In one aspect, the invention is directed towards a nut having a proteinaceous or fruit-based coating with no visible scorching in the outer, visible coating layer. In one aspect, the food center is par-coated with or without a heat susceptible coating, pre-roasted, finished coated with or without a heat susceptible coating, and cooked. In another aspect, the food center is first coated with a heat susceptible coating, then coated with a non-heat susceptible coating and cooked. In yet another aspect, the food center is coated with a heat susceptible coating and then cooked in a two-stage process whereby the first stage is at a hotter temperature than the second stage. | 07-30-2009 |
20090280224 | PROCESS FOR PRODUCING BAKED POTATO SLICES WITH EXPANDED TEXTURE - A method is disclosed for producing a baked snack chip made from a raw potato slice. The snack chip has a light, crispy, expanded texture similar to the texture of a fried potato chip. It is formed by compressing and heating a partially dried potato slice and then expanding the potato slice. Alternatively, the expanded potato slice is compressed again. | 11-12-2009 |
20100098829 | FRUIT AND VEGETABLE SNACKS - The present invention discloses formulations for vacuum baked fruit and vegetable snack pieces that have a crispy, crunchy texture similar to potato chip, corn based wafers, and other popular snack items. A fruit or vegetable base is combined with other ingredients and water to make a slurry, which is sheeted and dried in a vacuum belt dryer, and separated into snack sized pieces. In one embodiment, substantial amounts of solid inclusions are combined with the slurry before drying. | 04-22-2010 |
20110076381 | PROCESS FOR PRODUCING BAKED POTATO SLICES WITH EXPANDED TEXTURE - A method is disclosed for producing a baked snack chip made from a raw potato slice. The snack chip has a light, crispy, expanded texture similar to the texture of a fried potato chip. It is formed by compressing and heating a partially dried potato slice and then expanding the potato slice. Alternatively, the expanded potato slice is compressed again. | 03-31-2011 |
20120015091 | DIRECT EXPANDED SNACK MADE WITH PEANUT FLOUR AND METHOD FOR MAKING - A method for making a direct expanded snack piece shaped like a peanut is disclosed. Ingredients comprising peanut flour, ground corn product, rice flour and oat flour are introduced into an extruder. The ingredients are hydrated and extruded through an orifice adapted to produce a puffed snack piece shaped like a peanut and cut into puffed snacks. The puffed snacks are dried and seasoned. | 01-19-2012 |
20120093993 | METHOD FOR IMPROVING THE TEXTURAL ATTRIBUTES OF A BAKED SNACK FOOD - A method improving the textural attributes of baked snack foods. The method comprises mixing ingredients, extruding the ingredients to form a collet, hydrating the collet with a hydrating fluid to form a hydrated collet, and baking the hydrated collet. The hydrating fluid can comprise water, oil, a surfactant, an emulsifier, and mixtures thereof. In one embodiment the baking comprises utilizing an impingement oven. The method discussed herein more resembles the taste and texture of a fried product than does prior art baking methods. | 04-19-2012 |
20120114805 | SALTED FOOD PRODUCT - The invention allows for a reduction in the amount of salt topically applied to a food product with an oil layer on its outer surface, without adversely affecting the taste of the food product. Salt particles with a particle size greater than the thickness of the oil layer are topically applied to the food product. Because substantially all of the salt particles protrude from the oil layer, they provide a saltiness perception having no meaningful difference from the saltiness perception provided by a control salt applied at higher levels. | 05-10-2012 |
20120196021 | Fruit and Vegetable Snacks - The present invention discloses formulations for vacuum baked fruit and vegetable snack pieces that have a crispy, crunchy texture similar to potato chip, corn based wafers, and other popular snack items. A fruit or vegetable base is combined with other ingredients and water to make a slurry, which is sheeted and dried in a vacuum belt dryer, and separated into snack sized pieces. In one embodiment, substantial amounts of solid inclusions are combined with the slurry before drying. | 08-02-2012 |
20130045317 | Method and Formulation for Producing Extruded Snack Food Products and Products Obtained Therefrom - The present invention generally relates to the production of direct expanded farinaceous food products without the use of a drying apparatus such as an oven and without the use of traditionally used sugar to eliminate such drying steps. A farinaceous material combined with a plasticizer component in the form of trehalose is extruded to form a direct expanded shelf-stable snack food product. Snack food products made with trehalose can be incorporated into an outer shell of a composite center-filled or co-extruded product. | 02-21-2013 |
20140186509 | Baked Snack Food Product With Improved Textural Attributes - Baked snack food product with improved textural attributes. The method for making the baked snack food product comprises mixing ingredients, extruding the ingredients to form a collet, hydrating the collet with a hydrating fluid to form a hydrated collet, and baking the hydrated collet. The hydrating fluid can comprise water, oil, a surfactant, an emulsifier, and mixtures thereof In one embodiment the baking comprises utilizing an impingement oven. The method discussed herein more resembles the taste and texture of a fried product than does prior art baking methods. | 07-03-2014 |