Ranganathan, CA

Ananth Ranganathan, Santa Clara, CA US

Patent application number	Description	Published
20140343842	LOCALIZATION USING ROAD MARKINGS - One or more embodiments of techniques or systems for creating a road marking classification template and vehicle localization using road markings are provided herein. A road marking classification template database includes templates of training images taken from different navigation environments. A training image with a road marking can be rectified and enhanced. Corners can be calculated for the road marking using the rectified or enhanced image. Locations can be determined for the corners and stored as part of a template. Similarly, a runtime image can also be rectified, enhanced, boosted, etc. Additionally, corners can be calculated for the runtime image and matched against corners of templates from the template database. A location or a pose of a vehicle can be determined using the match. In this way, vehicle localization is provided such that drift or other issues associated with GPS, such as occlusion, are mitigated, for example.	11-20-2014
20150228077	SYSTEM AND METHOD FOR MAPPING, LOCALIZATION AND POSE CORRECTION - A system and method for mapping, localization and pose correction including, determining a current position of a vehicle along a travel route and a set of currently observable landmarks along the travel route relative to the current position, the set of currently observable landmarks extracted from one or more stereo images obtained from an imaging device, and querying a survey landmark database to identify a subset of surveyed landmarks relative to the current position of the vehicle. The method including determining one or more two-dimensional transform estimates between the set of currently observable landmarks and the subset of surveyed landmarks and identifying a best transform estimate from the one or more two-dimensional transform estimates that minimizes distances between the set of currently observable landmarks and the subset of surveyed landmarks. The method including correcting a pose of the vehicle based on the best transform estimate.	08-13-2015

Ananth Ranganathan, Mountain View, CA US

Patent application number	Description	Published
20100310159	SEMANTIC SCENE SEGMENTATION USING RANDOM MULTINOMIAL LOGIT (RML) - A system and method are disclosed for learning a random multinomial logit (RML) classifier and applying the RML classifier for scene segmentation. The system includes an image textonization module, a feature selection module and a RML classifier. The image textonization module is configured to receive an image training set with the objects of the images being pre-labeled. The image textonization module is further configured to generate corresponding texton images from the image training set. The feature selection module is configured to randomly select one or more texture-layout features from the texton images. The RML classifier comprises multiple multinomial logistic regression models. The RML classifier is configured to learn each multinomial logistic regression model using the selected texture-layout features. The RML classifier is further configured to apply the learned regression models to an input image for scene segmentation.	12-09-2010
20110229031	DETECTING AND LABELING PLACES USING RUNTIME CHANGE-POINT DETECTION AND PLACE LABELING CLASSIFIERS - A system and method are disclosed for detecting and labeling places in a video stream using change-points detection. The system comprises a place label generation module configured to assign place labels probabilistically to places in the video stream based on the measurements of the measurement stream representing the video. For each measurement in the segment, the place label generation module classifies the measurement by computing the probability of the measurement being classified by a learned Gaussian Process classifier. Based on the probabilities generated with respect to all the measurements in the segment, the place label generation module determines the place label for the segment. In cases where a Gaussian Process classifier cannot positively classify a segment, the place label generation module determines whether the segment corresponds to an unknown place based on the perplexity statistics of the classification and a threshold value.	09-22-2011
20110229032	Detecting And Labeling Places Using Runtime Change-Point Detection - A system and method are disclosed for detecting and labeling places recognized in a video stream using change-points detection. The system includes a segmentation module and a label learning module. The segmentation module is configured to receive a video stream comprising multiple digital representations of images. The video stream is represented by a measurement stream comprising one or more image histograms of the video stream. The segmentation module segments the measurement stream into multiple segments corresponding to place recognized in the videos stream. The segmentation module detects change-points of the measurement stream and computes probability distributions of the segments over multiple pre-learned place models. The label generation module is configured to generate place labels for the places recognized by the place models.	09-22-2011
20130279800	LEARNING PART-BASED MODELS OF OBJECTS - A system and method are disclosed for learning part-based object models during a learning phase from training images and applying the learned object models to an input image during runtime. The learned part-based object models are augmented by appearance-based models of the objects. The part-based object models correspond to the shapes of the parts of an object. The appearance-based models provide additional appearance cues to the object models for object classification. The approach to learning part-based object models has the capability of learning object models without using viewpoint labels of the objects. The learning is also invariant to scale and in-plane rotation of the objects.	10-24-2013
20140003709	ROAD MARKING DETECTION AND RECOGNITION	01-02-2014

Arun K. Ranganathan, San Francisco, CA US

Patent application number	Description	Published
20080209339	PERSONALIZATION TECHNIQUES USING IMAGE CLOUDS - Systems and methods for personalization using image clouds to represent content. Image clouds can be used to identify initial user interest, present recommended content, present popular content, present search results, and present user profile information. Image clouds are interactive, allowing users to select images displayed in the image cloud, which can contribute to presenting more personalized content as well as updating a user's profile.	08-28-2008
20080209340	PEER-TO-PEER ACCESS OF PERSONALIZED PROFILES USING CONTENT INTERMEDIARY - A method for personalizing content for a particular user in a computing system comprising a user interface configured to display content. The method comprises identifying a content item accessed by a user, identifying features associated with the content item; using the features of the content item to identify one or more third party profiles that substantially match a content profile of the content item, and displaying a list of the identified third party profiles.	08-28-2008
20140108954	PEER-TO-PEER ACCESS OF PERSONALIZED PROFILES USING CONTENT INTERMEDIARY - A method for personalizing content for a particular user in a computing system comprising a user interface configured to display content. The method comprises identifying a content item accessed by a user, identifying features associated with the content item; using the features of the content item to identify one or more third party profiles that substantially match a content profile of the content item, and displaying a list of the identified third party profiles.	04-17-2014
20150379146	PEER-TO-PEER ACCESS OF PERSONALIZED PROFILES USING CONTENT INTERMEDIARY - A method for personalizing content for a particular user in a computing system comprising a user interface configured to display content. The method comprises identifying a content item accessed by a user, identifying features associated with the content item; using the features of the content item to identify one or more third party profiles that substantially match a content profile of the content item, and displaying a list of the identified third party profiles.	12-31-2015

Gaurav Ranganathan, San Jose, CA US

Patent application number	Description	Published
20160063014	METHODS AND SYSTEMS FOR CREATING AND REMOVING VIRTUAL MACHINE SNAPSHOTS BASED ON GROUPS OF METRICS - Techniques are described herein which minimize the impact of virtual machine snapshots on the performance virtual machines and hypervisors. In the context of a volume snapshot which may involve (i) taking virtual machine snapshots of all virtual machines associated with the volume, (ii) taking the volume snapshot, and (iii) removing all the virtual machine snapshots, the virtual machine snapshots may be created in a first order and removed in a second order. Specifically, snapshots for busy virtual machines (i.e., virtual machines with higher disk write activity) may be created last and removed first. Consequently, snapshots of busy virtual machines are retained for the shorter periods of time, thereby minimizing the effect of virtual machine snapshots on those virtual machines (and their associated hypervisors) that would be most negatively impacted by virtual machine snapshots.	03-03-2016
20160103738	METHODS AND SYSTEMS FOR CONCURRENTLY TAKING SNAPSHOTS OF A PLURALITY OF VIRTUAL MACHINES - Techniques are described herein which minimize the impact of virtual machine snapshots on the performance of virtual machines and hypervisors. In the context of a volume snapshot which may involve (i) taking virtual machine snapshots of all virtual machines associated with the volume, (ii) taking the volume snapshot, and (iii) removing all the virtual machine snapshots, multiple virtual machine snapshots may be created in parallel. In the process of creating virtual machine snapshots, a storage system may determine which snapshots to create in parallel. The storage system may also prioritize snapshots from certain hypervisors in order to avoid the problem of “starvation”, in which busy hypervisors prevent less busy hypervisors from creating snapshots. The techniques described herein, while mainly described in the context of snapshot creation, are readily applied to snapshot removal.	04-14-2016

Jairam Ranganathan, Los Angeles, CA US

Patent application number	Description	Published
20130298125	EFFICIENT RECONSTRUCTION OF VIRTUAL DISK HIERARCHIES ACROSS STORAGE DOMAINS - A method and software is described for recreating on a target datastore a set of hierarchical files that are present on a source datastore. A content identifier (ID) is maintained for each component of the set of hierarchical files. The content ID of a component is updated when its contents are modified. The child component is copied from the source datastore to the target datastore. The content ID corresponding to the parent component on the source datastore is compared with content IDs corresponding to files present on the target datastore. When a matching content ID is discovered, it infers a copy of the parent component. The matching file on the target datastore is associated with the copied child component so that the matching file becomes a new parent component to the copied child component, thereby recreating the set of hierarchical files on the target.	11-07-2013

Jairam Ranganathan, San Francisco, CA US

Patent application number	Description	Published
20090037680	ONLINE VIRTUAL MACHINE DISK MIGRATION - A method for migrating a virtual machine disk (VM disk) from first physical storage to second physical storage while the virtual machine (VM) is running, the method comprising: (a) taking a snapshot of the VM disk as represented by a first parent VM disk stored on the first physical storage, whereby a first child VM disk is created on one of the first or second physical storage; (b) copying the first parent VM disk to the second physical storage as a second parent VM disk; (c) re-parenting the first VM child disk to the second parent VM disk; and (d) consolidating the first child VM disk and the second parent VM disk.	02-05-2009
20100299368	Efficient Reconstruction of Virtual Disk Hierarchies Across Storage Domains - A method and software is described for recreating on a target datastore a set of hierarchical files that are present on a source datastore. A content identifier (ID) is maintained for each component of the set of hierarchical files. The content ID of a component is updated when its contents are modified. The child component is copied from the source datastore to the target datastore. The content ID corresponding to the parent component on the source datastore is compared with content IDs corresponding to files present on the target datastore. When a matching content ID is discovered, it infers a copy of the parent component. The matching file on the target datastore is associated with the copied child component so that the matching file becomes a new parent component to the copied child component, thereby recreating the set of hierarchical files on the target.	11-25-2010
20120278573	ONLINE VIRTUAL MACHINE DISK MIGRATION - A method for migrating a virtual machine disk (VM disk) from first physical storage to second physical storage while the virtual machine (VM) is running, the method comprising: (a) taking a snapshot of the VM disk as represented by a first parent VM disk stored on the first physical storage, whereby a first child VM disk is created on one of the first or second physical storage; (b) copying the first parent VM disk to the second physical storage as a second parent VM disk; (c) re-parenting the first VM child disk to the second parent VM disk; and (d) consolidating the first child VM disk and the second parent VM disk.	11-01-2012

Karthik Ranganathan, Fremont, CA US

Patent application number	Description	Published
20140188825	PLACEMENT POLICY - A region-based placement policy that can be used to achieve a better distribution of data in a clustered storage system is disclosed herein. The clustered storage system includes a master module to implement the region-based placement policy for storing one or more copies of a received data across many data nodes of the clustered storage system. When implementing the region-based placement policy, the master module splits the received data into one or more regions, where each region includes a contiguous portion of the received data. Further, for each of the plurality of regions, the master module stores complete copies of the region in a subset of the data nodes.	07-03-2014

Krishnakumar Ranganathan, Oak Park, CA US

Patent application number	Description	Published
20100081786	Homogeneous Erythropoietin and Other Peptides and Proteins, Methods and Intermediates for Their Preparation - The present invention provides isolated homogeneous polyfunctionalized proteins (e.g., erythropoietin), isolated glycopeptides, and a method for preparing polyfunctionalized peptides and/or proteins via cysteine-free native chemical ligation. In certain embodiments, the invention provides an isolated homogeneous polyfunctionalized protein having the structure (I). In certain other embodiments, the invention provides an isolated glycopeptide having Formula (II). In certain other embodiments, the inventive method is a method for preparing a polyfunctionalized peptide comprising a peptidic backbone made up of four or more amino acids, wherein two or more non-adjacent amino acids are independently substituted with a moiety having the structure (III)-LH. wherein A and L1 are as defined herein.	04-01-2010

Lavakumar Ranganathan, San Diego, CA US

Patent application number	Description	Published
20120212245	CIRCUIT AND METHOD FOR TESTING INSULATING MATERIAL - An integrated circuit is disclosed. The integrated circuit includes an insulating material layer. The integrated circuit also includes a metal structure. Furthermore, the integrated circuit includes a via through the insulating material layer that is coupled to the metal structure for testing insulating material by applying dynamic voltage switching to two adjacent metal components of the metal structure.	08-23-2012
20150380325	PHYSICAL LAYOUT FEATURES OF INTEGRATED CIRCUIT DEVICE TO ENHANCE OPTICAL FAILURE ANALYSIS - An integrated circuit device includes an active silicon layer, and at least one passive metal layer placed in an input region and an output region of the device. The at least one passive metal layer has a surface area and thickness for at least one of the input region or the output region to provide a phase shift of an optical laser, the phase shift corresponding to an optimized visibility of the optical laser during an optic failure analysis of the device.	12-31-2015

Mukundan Ranganathan, San Diego, CA US

Nadeepuram K. Ranganathan, Irvine, CA US

Patent application number	Description	Published
20110071249	Fast-Drying Ink Composition - A fast-drying ink composition comprising water, a fast-drying solvent mixture including a hydrophilic co-solvent having low enthalpy of evaporation, a surface-active humectant, and a colorant. The hydrophilic co-solvent may be selected from the group consisting of propylene glycol n-propyl ether, tripropylene glycol methyl ether, and dipropylene glycol methyl ether. The surface-active humectant may comprise a hydrophobic end having a repeating unit “n” ranging from 1 to 36 and selected from the group consisting of alkane-based (CH	03-24-2011
20130080049	System and Method for Tracking Lost Subjects - A system and method for monitoring and tracking the position of a subject comprises, in an exemplary embodiment, a transponder configured for being co-located with the subject and a means for enabling communication between the transponder and a remote GPS-enabled receiver, such as a cell phone or the like, for selectively triangulating the position of the transponder. In the exemplary embodiment, the means for enabling such communication is software that is installed in and executed by the receiver. The software allows the receiver to triangulate the geographic position of the transponder by fixing a first reference point based on the location of the GPS-enabled receiver, fixing a second reference point based on the location of a network broadcast site through which the receiver and transponder communicate, and calculating the location of the transponder based on the angular position of the transponder relative to the network broadcast site.	03-28-2013

Partha Ranganathan, San Jose, CA US

Patent application number	Description	Published
20110246828	Memory Checkpointing Using A Co-Located Processor and Service Processor - A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.	10-06-2011
20120136909	CLOUD ANOMALY DETECTION USING NORMALIZATION, BINNING AND ENTROPY DETERMINATION - Illustrated is a system and method for anomaly detection in data centers and across utility clouds using an Entropy-based Anomaly Testing (EbAT), the system and method including normalizing sample data through transforming the sample data into a normalized value that is based, in part, on an identified average value for the sample data. Further, the system and method includes binning the normalized value through transforming the normalized value into a binned value that is based, in part, on a predefined value range for a bin such that a bin value, within the predefined value range, exists for the sample data. Additionally, the system and method includes identifying at least one vector value from the binned value. The system and method also includes generating an entropy time series through transforming the at least one vector value into an entropy value to be displayed as part of a look-back window.	05-31-2012

Partha Ranganathan, Fremont, CA US

Patent application number	Description	Published
20090271646	Power Management Using Clustering In A Multicore System - A multi-core system including cores and voltage sources supplying power to the cores. The cores are divided into clusters based on the particular voltage source supplying power to each core. Power management is performed in the multi-core system based on one or more of core utilization and a management policy.	10-29-2009
20100332720	Direct Memory Access and Super Page Swapping Optimizations For A Memory Blade - A system and method is illustrated for identifying an Input/Output (I/O) driver module, using a hypervisor, to receive a read command to read a virtual memory page from a remote memory location. Further, the system and method includes reading the remote virtual memory page, using the I/O driver module, into a memory buffer managed by the I/O driver module. Additionally, the system and method includes storing the virtual memory page in the memory buffer to a persistent storage device. The system and method also includes identifying a remote super page, using a hypervisor, the remote super page including a remote sub page. Additionally, the system and method includes identifying a local super page, using the hypervisor, the local super page including a local sub page. Further, the system and method includes swapping the local sub page for the remote sub page, using the hypervisor, the swapping occurring over a network.	12-30-2010
20110007746	Establishing Network Quality of Service for a Virtual Machine - A system and method for implementing a VM to identify a data packet for transmission, the data packet including a QoS the data packet is to receive as compared to another QoS that another data packet is to receive. The system and method further includes a SNIC to pull the data packet from the VM based upon the QoS the data packet is to receive. The system and method may also include a link scheduler module to transmit the data packet based upon the QoS the data packet is to receive. The system and method may also include a receiver to receive a management instruction from a network management device, the management instruction to dictate the QoS the data packet is to receive based upon a SLA.	01-13-2011
20110010721	Managing Virtualized Accelerators Using Admission Control, Load Balancing and Scheduling - A system and method is shown that includes an admission control module that resides in a management/driver domain, the admission control module to admit a domain that is part of a plurality of domains, into the computer system based upon one of a plurality of accelerators satisfying a resource request of the domain. The system and method also includes a load balancer module, which resides in the management/driver domain, the load balancer to balance at least one load from the plurality of domains across the plurality of accelerators. Further, the system and method also includes a scheduler module that resides in the management/driver domain, the scheduler to multiplex multiple requests from the plurality of domains to one of the plurality of accelerators.	01-13-2011
20120005556	Organizing And Managing A Memory Blade With Super Pages And Buffers - A system and method is illustrated wherein a protocol agent module receives a memory request encoded with a protocol, the memory request identifying an address location in a memory module managed by a buffer. Additionally, the system and method includes a memory controller to process the memory request to identify the buffer that manages the address location in the memory module. Further, the system and method includes an address mapping module to process the memory request to identify at least one super page associated with the memory module, the at least one super page associated with the address location.	01-05-2012
20120030406	HYPERVISOR-BASED MANAGEMENT OF LOCAL AND REMOTE VIRTUAL MEMORY PAGES - A system and method is illustrated for comparing a target memory address and a local memory size using a hypervisor module that resides upon a compute blade, the comparison based upon a unit of digital information for the target memory address and an additional unit of digital information for the local memory size. Additionally, the system and method utilizes swapping of a local virtual memory page with a remote virtual memory page using a swapping module that resides on the hypervisor module, the swapping based upon the comparing of the target memory address and the local memory size. Further, the system and method is implemented to transmit the local virtual memory page to a memory blade using a transmission module that resides upon the compute blade.	02-02-2012

Parthasarathy Ranganathan, San Jose, CA US

Patent application number	Description	Published
20110213838	MANAGING AT LEAST ONE COMPUTER NODE - In a system for managing at least one computer node, a first device is configured to perform out-of-band operations in the at least one computing node. The system also includes a second device configured to perform compute-intensive tasks in the at least one computing node and a third device that is external to the at least one computing node configured to perform administration operations for the first device and the second device.	09-01-2011
20110307679	MANAGING WEAR ON INDEPENDENT STORAGE DEVICES - In a method of managing wear on a plurality of independent storage devices having respective sets of memory cells, access characteristics of the memory cells in the plurality of independent storage devices are monitored. In addition, an instruction to access data on at least one of the memory cells is received and an independent storage device of the plurality of independent storage devices is selected to access data on at least one of the memory cells of the selected independent storage device based upon one or more predetermined selection policies and the monitored access characteristics of the memory cells in the plurality of independent storage devices. Moreover, the selected independent storage device is assigned to access data on at least one of the memory cells of the selected independent storage device according to the received instruction.	12-15-2011
20110307899	COMPUTING CLUSTER PERFORMANCE SIMULATION USING A GENETIC ALGORITHM SOLUTION - Illustrated is a system and method that includes identifying a search space based upon available resources, the search space to be used to satisfy a resource request. The system and method also includes selecting from the search space an initial candidate set, each candidate of the candidate set representing a potential resource allocation to satisfy the resource request. The system and method further includes assigning a fitness score, based upon a predicted performance, to each member of the candidate set. The system and method also includes transforming the candidate set into a fittest candidate set, the fittest candidate set having a best predicted performance to satisfy the resource request.	12-15-2011
20120011401	DYNAMICALLY MODELING AND SELECTING A CHECKPOINT SCHEME BASED UPON AN APPLICATION WORKLOAD - Illustrated is a system and method for executing a checkpoint scheme as part of processing a workload using an application. The system and method also includes identifying a checkpoint event that requires an additional checkpoint scheme. The system and method includes retrieving checkpoint data associated with the checkpoint event. It also includes building a checkpoint model based upon the checkpoint data. The system and method further includes identifying the additional checkpoint scheme, based upon the checkpoint model, the additional checkpoint scheme to be executed as part of the processing of the workload using the application.	01-12-2012
20120087674	OPTICAL DATA PATH SYSTEMS - This disclosure is directed to optical data path systems that enable unidirectional and bidirectional transmission of optical signals between nodes of a multi-node system such as a multiprocessor system. In one aspect, an optical data path system includes an optical device layer connected to nodes of a multi-node system and a controller. The optical device layer includes a waveguide network of waveguide branches optically connecting each node of the multi-node system to every other node of the multi-node system, resonators disposed adjacent to the waveguide branches, and detectors disposed adjacent to waveguide branches of the waveguide network. Each detector is electronically connected to a node of the multi-node system. The resonators are operated by the controller to control the path of optical signals sent between the nodes of the multi-node system.	04-12-2012
20120131278	DATA STORAGE APPARATUS AND METHODS - Data storage apparatus and methods are disclosed. A disclosed example data storage apparatus comprises a cache layer and a processor in communication with the cache layer. The processor is to dynamically enable or disable the cache layer via a cache layer enable line based on a data store access type.	05-24-2012
20120185727	COMPUTING SYSTEM RELIABILITY - Systems, methods, and computer-readable and executable instructions are provided for computing system reliability. A method for computing system reliability can include storing, on one of a plurality of devices, a checkpoint of a current state associated with the one of the plurality of devices. The method may further include storing the checkpoint in an erasure-code group across the plurality of devices.	07-19-2012
20120203381	MANAGING AN INFRASTRUCTURE HOUSING DISAGGREGATED HEAT SOURCES - In a method for managing an infrastructure housing a plurality of disaggregated heat sources, in which a first disaggregated heat source has different heat dissipation characteristics as compared with a second disaggregated heat source, cooling requirements for the disaggregated heat sources are determined, in which the first disaggregated heat source and the second disaggregated heat source are to be positioned in separate homogeneous zones of the infrastructure. In addition, a respective available cooling resource is associated with the disaggregated heat sources based upon the determined cooling requirements of the disaggregated heat sources.	08-09-2012
20120210042	REMOTE MEMORY FOR VIRTUAL MACHINES - Remote memory can be used for a number idle pages located on a virtual machine. A number of idle pages can be sent to the remote memory according to a placement policy, where the placement policy can include a number of weighting factors. A hypervisor on a computing device can record a local size and a remote page fault frequency of the number of virtual machines. The hypervisor can scan local memory to determine the number of idle pages and a number of idle virtual machines. The number of idle pages, including a page map and a remote address destination for each idle page, can be sent to the remote memory by the hypervisor. The number of virtual machines can be analyzed to determine a per-virtual machine local memory allocation.	08-16-2012
20120233472	SECURING NON-VOLATILE MEMORY REGIONS - Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.	09-13-2012
20120239799	NETWORK SYSTEM MANAGEMENT - Systems, methods, and machine-readable and executable instructions are provided for network system management. Network system management can include receiving a network system size and a number of system parameters. Network system management can also include receiving a desired monitoring performance and a desired monitoring quality. Furthermore, network system management can include generating a monitoring system topology for a monitoring and analysis system based on the network system size, the number of system parameters, the desired monitoring performance, and the desired monitoring quality.	09-20-2012
20120254507	WRITE-ABSORBING BUFFER FOR NON-VOLATILE MEMORY - A write-absorbing, volatile memory buffer for use with a processor module and a non-volatile memory is disclosed. The write-absorbing buffer operates as a dirty cache that can be used to look up both read and write requests, although allocating new blocks only for write requests and not read requests. The blocks are small sized, and a write-only least-recently used cache replacement policy is used to transfer data in the blocks to the non-volatile memory. The write-absorbing buffer can be used to store copy-on-write pages for at least one virtual machine associated with the processor module and reduce write overhead to the non-volatile memory.	10-04-2012
20120268983	RANDOM-ACCESS MEMORY WITH DYNAMICALLY ADJUSTABLE ENDURANCE AND RETENTION - A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality.	10-25-2012
20120272036	ADAPTIVE MEMORY SYSTEM - An adaptive, memory system is provided. The adaptive memory system has a number of physical-memory devices and a memory controller that creates and maintains a logical address space to which the physical-memory devices and data-storage allocations are mapped, and through which mapping the memory controller matches static, dynamic, and dynamically-adjustable retention and resiliency characteristics of portions of the physical-memory devices with specified retention and resiliency characteristics specified for the data-storage allocations.	10-25-2012
20120272039	RETENTION-VALUE ASSOCITED MEMORY - A memory component or subsystem is provided. The memory comprises one or more memory devices and one or more write controllers within each of the one or more memory devices that each controls memory-device components to write input data values into a plurality of memory cells within a memory device that represents a unit of stored data addressed by a logical-address-space address, the write controller applying a current to the plurality of memory cells during a WRITE operation with a magnitude that corresponds to a retention value associated with the logical-address-space address.	10-25-2012
20120278650	CONTROLLING NANOSTORE OPERATION BASED ON MONITORED PERFORMANCE - Methods, apparatus and articles of manufacture for controlling nanostore operation based on monitored performance are disclosed. An example method disclosed herein comprises monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic, and controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore.	11-01-2012
20120278651	Remapping data with pointer - Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block.	11-01-2012
20130046904	MANAGEMENT PROCESSORS, METHODS AND ARTICLES OF MANUFACTURE - Example management processors, methods and articles of manufacture are disclosed. A disclosed example management processor includes a network card interface to communicatively couple the management processor to an operating environment, and a request processor to forward a received external management request to the operating environment via the network card interface, and to combine response information received from the operating environment with response information generated at the management processor.	02-21-2013
20130094138	COMPUTER RACKS - Example computer racks to improve environmental sustainability in data centers are disclosed. An example computer rack includes a spine (	04-18-2013
20130111107	TIER IDENTIFICATION (TID) FOR TIERED MEMORY CHARACTERISTICS	05-02-2013
20130111249	ACCESSING A LOCAL STORAGE DEVICE USING AN AUXILIARY PROCESSOR	05-02-2013
20130227218	Data Migration between Memory Locations - Migrating data may include determining to copy a first data block in a first memory location to a second memory location and determining to copy a second data block in the first memory location to the second memory location based on a migration policy.	08-29-2013
20130246731	DISTRIBUTED GRAPH STORAGE SYSTEM - In a method of implementing a graph storage system, the graph storage system is stored on a plurality of computing systems. A global address space is provided for distributed graph storage. The global address space is managed with graph allocators, in which a graph allocator allocates space from a block of the distributed global memory in order to store a plurality of graphs.	09-19-2013
20130290607	STORING CACHE METADATA SEPARATELY FROM INTEGRATED CIRCUIT CONTAINING CACHE CONTROLLER - A technique includes using a cache controller of an integrated circuit to control a cache including cached data content and associated cache metadata. The technique includes storing the metadata and the cached data content off of the integrated circuit and organizing the storage of the metadata relative to the cached data content such that a bus operation initiated by the cache controller to target the cached data content also targets the associated metadata.	10-31-2013
20130290650	DISTRIBUTED ACTIVE DATA STORAGE SYSTEM - A request from a requestor identifies data stored in a distributed active data storage system and a procedure that is associated with the identified data for a given node of the distributed active data storage system to execute. The execution of the procedure causes the given node to selectively determine an address for routing another request to an element of a plurality of elements of a data structure stored on the plurality of nodes.	10-31-2013
20130290911	METHOD AND SYSTEM FOR MULTIMODAL AND GESTURAL CONTROL - Embodiments of the present invention disclose a multimodal and gestural control system. According to one embodiment, the multimodal and gestural control system is configured to detect a gesture command from a user via at least one device of a plurality of devices. A control operation and a destination device are both determined based on the gesture command such that the determined control operation is executed on the determined destination device.	10-31-2013
20130329491	Hybrid Memory Module - A hybrid. memory module. The module includes at least two heterogeneous memory devices and a memory buffer in communication with the memory devices to read data from any one of the memory devices and write the data to any other of the memory devices.	12-12-2013
20130339468	NON-VOLATILE MEMORY PHYSICAL NETWORKS - A method for communication between computing devices includes identifying the parameters of a data transfer between a source computing device and a target computing device and identifying communication paths between a source computing device and target computing device, in which at least one of the communications paths is a physical network. A communication path is selected for the data transfer. When a data transfer over the physical network is selected as a communication path, a nonvolatile memory (NVM) unit is removed from the source computing device and placed in a cartridge and the cartridge is programmed with transfer information. The NVM unit and cartridge are transported through the physical network to the target computing device according to the transfer information and the NVM unit is electrically connected to the target computing device.	12-19-2013
20140013054	STORING DATA STRUCTURES IN CACHE - A method and system for implementing a data structure cache are provided herein. The method includes identifying a data structure. The method also includes identifying a plurality of frequently accessed data blocks in the data structure. Additionally, the method includes reserving a portion of a cache for storage of the frequently accessed data blocks. Furthermore, the method includes storing the frequently accessed data blocks in the reserved portion of the cache.	01-09-2014
20140019677	STORING DATA IN PRESISTENT HYBRID MEMORY - Storing data in persistent hybrid memory includes promoting a memory block from non-volatile memory to a cache based on a usage of said memory block according to a promotion policy, tracking modifications to the memory block while in the cache, and writing the memory block back into the non-volatile memory after the memory block is modified in the cache based on a writing policy that keeps a number of the memory blocks that are modified at or below a number threshold while maintaining the memory block in the cache.	01-16-2014
20140032818	PROVIDING A HYBRID MEMORY - A hybrid memory has a volatile memory and a non-volatile memory. The volatile memory is dynamically configurable to have a first portion that is part of a memory partition, and a second portion that provides a cache for the non-volatile memory.	01-30-2014
20140033214	MANAGING ARRAY COMPUTATIONS DURING PROGRAMMATIC RUN-TIME IN A DISTRIBUTED COMPUTING ENVIRONMENT - A plurality of array partitions are defined for use by a set of tasks of the program run-time. The array partitions can be determined from one or more arrays that are utilized by the program at run-time. Each of the plurality of computing devices are assigned to perform one or more tasks in the set of tasks. By assigning each of the plurality of computing devices to perform one or more tasks, an objective to reduce data transfer amongst the plurality of computing devices can be implemented.	01-30-2014
20140040528	RECONFIGURABLE CROSSBAR NETWORKS - Reconfigurable crossbar networks, and devices, systems and methods, including hardware in the form of logic (e.g. application specific integrated circuits (ASICS)), and software in the form of machine readable instructions stored on machine readable media (e.g., flash, non-volatile memory, etc.), which implement the same, are provided. An example of a reconfigurable crossbar network includes a crossbar. A plurality of endpoints is coupled to the crossbar. The plurality of endpoints is grouped into regions at design time of the crossbar network. A plurality of regional interconnects are provided. Each regional interconnect connects a group of endpoints within a given region.	02-06-2014
20140122807	MEMORY ADDRESS TRANSLATIONS - Memory address translations are disclosed. An example memory controller includes an address translator to translate an intermediate memory address into a hardware memory address based on a function, the address translator to select the function based on at least a portion of the intermediate memory address, the intermediate memory address being identified by a processor. The example memory controller includes a cache to store the function in association with an address range of the intermediate memory sector, the intermediate memory address being within the intermediate memory sector. Further, the example memory controller includes a memory accesser to access a memory module at the hardware memory address.	05-01-2014
20140215158	Executing Requests from Processing Elements with Stacked Memory Devices - Executing requests from processing elements with stacked memory devices includes receiving a request from a processing element, determining which of multiple memory devices contains information pertaining to the request, forwarding the request to a selected memory device of the memory devices, and responding to the processing element with the information in response to receiving the information from the selected memory device.	07-31-2014
20140215160	METHOD OF USING A BUFFER WITHIN AN INDEXING ACCELERATOR DURING PERIODS OF INACTIVITY - A method of using a buffer within an indexing accelerator during periods of inactivity, comprising flushing indexing specific data located in the buffer, disabling a controller within the indexing accelerator, handing control of the buffer over to a higher level cache, and selecting one of a number of operation modes of the buffer. An indexing accelerator, comprising a controller and a buffer communicatively coupled to the controller, in which, during periods of inactivity, the controller is disabled and a buffer operating mode among a number of operating modes is chosen under which the buffer will be used.	07-31-2014
20140215260	MEMCACHED SERVER REPLICATION - According to an example, data for a memcached server is replicated to a memcached replication server. Data operations for the memcached server may be filtered for backing up data to the memcached replication server.	07-31-2014
20140351495	LOCAL CHECKPOINTING USING A MULTI-LEVEL CELL - Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint.	11-27-2014
20140351518	MULTI-LEVEL CACHE TRACKING TABLE - Disclosed herein are a computing system, integrated circuit, and method to enhance retrieval of cached data. A tracking table is used to initiate a search for data from a location specified in the table, if the data is not in a first level of a multi-level cache hierarchy.	11-27-2014
20150074250	NETWORK MANAGEMENT - A system and method for network management are described herein. The system includes a number of servers and a first network coupling the servers to each other and configured to connect the servers to one or more client computing devices. The system also includes a second network coupling the servers to each other, wherein data transferred between the servers is transferred though the second network. Network management requests for configuring the second network are communicated to the servers through the first network.	03-12-2015
20150074456	VERSIONED MEMORIES USING A MULTI-LEVEL CELL - Versioned memories using a multi-level cell (MLC) are disclosed. An example method includes comparing a global memory version to a block memory version, the global memory version corresponding to a plurality of memory blocks, the block memory version corresponding to one of the plurality of memory blocks. The example method includes determining, based on the comparison, which level in a multi-level cell of the one of the plurality of memory blocks stores checkpoint data.	03-12-2015
20150163172	SERVER SWITCH INTEGRATION IN A VIRTUALIZED SYSTEM - A switch, a system and operational method for packet switching between virtual machines running in a server and a network. The server comprises a switch with swappable, virtual ports. The switch routes packets to and from the various virtual machines resident in the server memory.	06-11-2015
20150186189	MANAGING ARRAY COMPUTATIONS DURING PROGRAMMATIC RUN-TIME IN A DISTRIBUTED COMPUTING ENVIRONMENT - A plurality of array partitions are defined for use by a set of tasks of the program run-time. The array partitions can be determined from one or more arrays that are utilized by the program at run-time. Each of the plurality of computing devices are assigned to perform one or more tasks in the set of tasks. By assigning each of the plurality of computing devices to perform one or more tasks, an objective to reduce data transfer amongst the plurality of computing devices can be implemented.	07-02-2015
20150254014	Storing Data in Persistent Hybrid Memory - Storing data in persistent hybrid memory includes promoting a memory block from non-volatile memory to a cache based on a usage of said memory block according to a promotion policy, tracking modifications to the memory block while in the cache, and writing the memory block back into the non-volatile memory after the memory block is modified in the cache based on a writing policy that keeps a number of the memory blocks that are modified at or below a number threshold while maintaining the memory block in the cache.	09-10-2015
20150324293	CONTROLLED CACHE INJECTION OF INCOMING DATA - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for pre-fetching data. The methods, systems, and apparatus include actions of providing a request for data to an input-output device and receiving a set of memory addresses for the requested data. Additional actions include determining a subset of the memory addresses, providing a request for a processor to pre-fetch or inject data corresponding to the subset of the memory addresses, and receiving the requested data and the set of memory addresses. Additional actions include determining that the received data includes data for the subset of memory addresses that has been requested to be pre-fetched or injected, storing the data for the subset of memory addresses in a cache of the processor, and storing remaining data of the received data for the memory addresses in a main memory.	11-12-2015

Parthasarathy Ranganathan, Palo Alto, CA US

Patent application number	Description	Published
20150193158	SMART MEMORY BUFFERS - An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.	07-09-2015
20150350381	Vertically-Tiered Client-Server Architecture - Systems and methods of vertically aggregating tiered servers in a data center are disclosed. An example method includes partitioning a plurality of servers in the data center to form an array of aggregated end points (AEPs). Multiple servers within each AEP are connected by an intra-AEP network fabric and different AEPs are connected by an inter-AEP network. Each AEP has one or multiple central hub servers acting as end-points on the inter-AEP network. The method includes resolving a target server identification (ID). If the target server ID is the central hub server in the first AEP, the request is handled in the first AEP. If the target server ID is another server local to the first AEP, the request is redirected over the intra-AEP fabric. If the target server ID is a server in a second AEP, the request is transferred to the second AEP.	12-03-2015
20160034528	CO-PROCESSOR-BASED ARRAY-ORIENTED DATABASE PROCESSING - A technique includes receiving a user input in an array-oriented database. The user input indicates a database operation and processing a plurality of chunks of data stored by the database to perform the operation. The processing in dudes selectively distributing the processing of the plurality of chunks between a first group of at least one central processing unit and a second group of at least one co-processor.	02-04-2016
20160062821	INVOKING AN ERROR HANDLER TO HANDLE AN UNCORRECTABLE ERROR - A detector detects, using an error code, an error in data stored in a memory. The detector determines whether the error is uncorrectable using the error code. In response to determining that the error is uncorrectable, an error handler associated with an application is invoked to handle the error in the data by recovering the data to an application-wide consistent state.	03-03-2016
20160070483	SEPARATE MEMORY CONTROLLERS TO ACCESS DATA IN MEMORY - A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.	03-10-2016
20160070701	INDEXING ACCELERATOR WITH MEMORY-LEVEL PARALLELISM SUPPORT - According to an example, an indexing accelerator with memory-level parallelism (MLP) support may include a request decoder to receive indexing requests. The request decoder may include a plurality of configuration registers. A controller may be communicatively coupled to the request decoder to support MLP by assigning an indexing request of the received indexing requests to a configuration register of the plurality of configuration registers. A buffer may be communicatively coupled to the controller to store data related to an indexing operation of the controller for responding to the indexing request.	03-10-2016
20160077922	Advanced Versioned Memory - According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.	03-17-2016

Prashanth Ranganathan, San Francisco, CA US

Patent application number	Description	Published
20120209773	FRAUD ALERTING USING MOBILE PHONE LOCATION - A location of a transaction or payment request is compared with a location of a user device to determine whether the distance is great enough to send an alert for a possible fraudulent transaction. The user device location may be predicted based on a last known location and information about the area of the last known location and movement of the user device.	08-16-2012
20120233665	DEVICE REPUTATION - A user device is associated with a dynamic trust score that may be updated as needed, where the trust score and the updates are based on various activities and information associated with the mobile device. The trust score is based on both parameters of the device, such as device type, registered device location, device phone number, device ID, the last time the device has been accessed, etc. and activities the device engages in, such as amount of transactions, dollar amount of transactions, amount of denied requests, amount of approved requests, location of requests, etc. Based on a transaction request from the user device, the trust score and a network reputation score is used to determine an overall trust/fraud score associated with the transaction request.	09-13-2012
20130173474	OFFLINE MOBILE PHONE PAYMENTS - A method for performing vending transactions includes generating a token upon request by a wireless appliance is provided. The method includes placing the token in a remote server; placing the token in the wireless appliance; providing the token from the wireless appliance to a point-of-sale (POS) terminal; authenticating the token with the remote server; validating the token to perform the vending transaction; and deleting the token from the remote server when the vending transaction is complete. A method for using a wireless appliance in vending transactions is provided. A method for using a remote server configured to connect to a wireless appliance and a POS terminal in vending transactions is provided. A system to perform vending transactions using an internet connection as above is provided. The system may include a remote server including a private account; the remote server configured to communicate with a POS terminal and a wireless appliance.	07-04-2013
20150095990	DEVICE REPUTATION - A user device is associated with a dynamic trust score that may be updated as needed, where the trust score and the updates are based on various activities and information associated with the mobile device. The trust score is based on both parameters of the device, such as device type, registered device location, device phone number, device ID, the last time the device has been accessed, etc. and activities the device engages in, such as amount of transactions, dollar amount of transactions, amount of denied requests, amount of approved requests, location of requests, etc. Based on a transaction request from the user device, the trust score and a network reputation score is used to determine an overall trust/fraud score associated with the transaction request.	04-02-2015

Prem Ranganathan, Fremont, CA US

Patent application number	Description	Published
20120072982	DETECTING POTENTIAL FRAUDULENT ONLINE USER ACTIVITY - One or more techniques and/or systems are disclosed herein for identifying potentially fraudulent use of user generated content (UGC) for an online activity by a user. Server-based information and browser-based information associated with the user is identified and used to create a user signature. The user signature is associated with the UGC for the online activity in a cache-key. The cache-key is compared to a desired threshold for identifying potentially fraudulent use of the UGC for the online activity, where potential fraud may be detected if the cache key meets the desired threshold.	03-22-2012

Ram Ranganathan, Palo Alto, CA US

Patent application number	Description	Published
20100107063	Automated visual analysis of nearby markings of a visualization for relationship determination and exception identification - To automatically visually analyze relationship in data records that are presented by a visualization containing cells representing corresponding data records, identification of a threshold of interest is received for a particular one of attributes in the visualization. Nearby areas in the visualization are marked based on the threshold, and data records in the marked areas are mined to determine at least one relationship between the particular attribute and at least one other attribute, and to identify information associated with an exception. A result of the mined at least one relationship is provided, for display, in a graphical element.	04-29-2010
20110298804	VISUAL DISPLAY OF DATA FROM A PLURALITY OF DATA SOURCES - Systems and methods are provided for viewing, aligning, and correlating data in a visual display from data sources in data management systems. In one method, data sources in a data management system can be identified. Data attributes from the data sources can be displayed together as graphical cells over a common timeline as a reference for cell attribute columns. A first graphical cell in an attribute column at a time position on the common timeline can be selected. The graphical cell can represent a data record for a time measurement interval. A second graphical cell can be aligned with the first graphical cell based on the time position. The second graphical cell can be positioned in a same cell column as the first graphical cell and represent data obtained at a substantially same time as the data represented by the first graphical cell.	12-08-2011
20130054776	AUTOMATED SCALING OF AN APPLICATION AND ITS SUPPORT COMPONENTS - An execution environment provides a plurality of components that support execution of an application, wherein the plurality of components and the application are hosted by a plurality of nodes arranged in one or more clusters. The execution environment monitors runtime behavior of the application and the plurality of components, and generates a scaling event based on a comparison of the runtime behavior to one or more scaling policies. The execution environment automatically scales at least one of the application or a component of the plurality of components if the scaling event does not violate a constraint, wherein the scaling comprises adding a new node to at least one cluster of the one or more clusters or removing a node from at least one cluster of the one or more clusters based on the scaling event.	02-28-2013
20130198718	AUTOMATED CONFIGURATION OF AN APPLICATION IN A COMPUTING PLATFORM - Upon receiving application code and an application descriptor of an application, a platform executing on a computer system identifies a capability to be used by the application based on the application descriptor. The platform determines a component that provides the capability based on a component descriptor of the component. The platform then configures the application and the component for execution on the platform.	08-01-2013
20130198763	CONNECTION MANAGEMENT FOR AN APPLICATION IN A COMPUTING PLATFORM - A computing device detects an event generated by a first component that publishes a connection endpoint, the event indicating that the connection endpoint of the first component has been modified. The computing device determines a second component that subscribes to the connection endpoint. The computing device updates a location of the connection endpoint in a data structure associated with the second component to maintain a connection between the first component and the second component.	08-01-2013

Ramachandran Ranganathan, Danville, CA US

Patent application number	Description	Published
20120258043	Linkable Lewis X Analogs - Disclosed herein is a class of linkable tetrasaccharide compounds that includes the amino phenyl glycoside of sialyl Lewis X (SLe	10-11-2012

Ramachandran Ranganathan, Kensington, CA US

Patent application number	Description	Published
20080300220	Linkable Lewis X Analogs - Disclosed herein is a class of linkable tetrasaccharide compounds that includes the amino phenyl glycoside of sialyl Lewis X (SLe	12-04-2008
20110229409	LINKABLE LEWIS X ANALOGS - Disclosed herein is a class of linkable tetrasaccharide compounds that includes the amino phenyl glycoside of sialyl Lewis X (SLe	09-22-2011

Ranjith Ranganathan, San Jose, CA US

Patent application number	Description	Published
20150198699	ULTRASONIC IMAGING WITH ACOUSTIC RESONANT CAVITY - Techniques describe structures and methods for generating larger output signals and improving image quality of ultrasonic sensors by inclusion of an acoustic cavity in the sensor stack. In some embodiments, an ultrasonic sensor unit may be tuned during manufacturing or during a provisioning phase to work with different thicknesses and materials. In some embodiments, a standing wave signal may be generated using an acoustic cavity in the ultrasonic sensor unit for capturing an ultrasonic image of an object placed on a sensor surface. In some implementations, the ultrasonic sensor may include an ultrasonic transmitter, a piezoelectric receiver, a thin film transistor (TFT) layer and a TFT substrate positioned between the transmitter and the receiver, one or more adhesive layers, and optional cover materials and coatings. The thickness, density and speed of sound of the sensor materials and associated adhesive attachment layers may be used to attain the desired acoustic cavity and improved performance.	07-16-2015

Ravi Ranganathan, Cupertino, CA US

Patent application number	Description	Published
20120188260	GRAPHICS CONTROLLER INTEGRATED CIRCUIT WITHOUT MEMORY INTERFACE - A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.	07-26-2012

Ravi Ranganathan, San Jose, CA US

Patent application number	Description	Published
20110157202	Techniques for aligning frame data - Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques attempt to avoid visible glitches when switching from displaying a frame from a first source to displaying frames from a second source even though alignment is achieved by switching if frames that are to be displayed from the second source are similar to those displayed from the first source.	06-30-2011

Ravi Ranganathan, Sunnyvale, CA US

Patent application number	Description	Published
20100123727	Techniques to control self refresh display functionality - Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.	05-20-2010
20110157198	Techniques for aligning frame data - Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.	06-30-2011
20120075188	TECHNIQUES TO CONTROL DISPLAY ACTIVITY - Techniques are described to transmit commands to a display device during vertical or horizontal blanking intervals. The commands can be transmitted using fields that would otherwise be used to transmit color information. A Low Voltage Differential Signaling (LVDS) compliant interface can be used to transmit the commands.	03-29-2012
20130021357	TECHNIQUES TO CONTROL OF SELF REFRESH DISPLAY FUNCTIONALITY - Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.	01-24-2013
20140104286	TECHNIQUES TO CONTROL SELF REFRESH DISPLAY FUNCTIONALITY - Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a. current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.	04-17-2014
20140104290	TECHNIQUES TO CONTROL SELF REFRESH DISPLAY FUNCTIONALITY - Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.	04-17-2014
20140111531	TECHNIQUES TO CONTROL SELF REFRESH DISPLAY FUNCTIONALITY - Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.	04-24-2014

Rohini Ranganathan, San Jose, CA US

Patent application number	Description	Published
20080308937	COPPER-FREE SEMICONDUCTOR DEVICE INTERFACE AND METHODS OF FABRICATION AND USE THEREOF - Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and an upper surface of the copper-free interface to facilitate electrical coupling of the substrate to a semiconductor device while physically isolating the semiconductor device from the copper-containing feature.	12-18-2008

Sridharan Ranganathan, San Ramon, CA US

Patent application number	Description	Published
20130262731	SUPERSPEED INTER-CHIP COMMUNICATIONS - An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.	10-03-2013
20130297833	CONFIGURING A REMOTE M-PHY - An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.	11-07-2013
20130318279	Providing A Load/Store Communication Protocol With A Low Power Physical Unit - In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.	11-28-2013
20140173164	Providing A Load/Store Communication Protocol With A Low Power Physical Unit - In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.	06-19-2014
20140289434	Leveraging an Enumeration and/or Configuration Mechanism of One Interconnect Protocol for a Different Interconnect Protocol - An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The interconnect architecture device also includes conversion logic coupled with the processor. The conversion logic is to convert the transaction, which is of the different interconnect protocol than LLI, to an LLI packet. The interconnect architecture device also includes an LLI controller coupled with the conversion logic. The LLI controller is to couple the interconnect architecture device with an LLI link. The LLI controller is to transmit the LLI packet on the LLI link.	09-25-2014
20150134866	SUPERSPEED INTER-CHIP INTERFACE - An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.	05-14-2015
20150212969	CONFIGURING A REMOTE M-PHY - An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.	07-30-2015
20150333735	BLOCK PARTITION TO MINIMIZE POWER LEAKAGE - Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal Serial Bus (USB) physical subsystem and system firmware, wherein the system firmware conveys USB related events to the SOC. The system is configured to include a power management apparatus, where the power management apparatus includes USB wake functionality and USB On-the-Go (OTG) functionality.	11-19-2015

Srikanth Ranganathan, Mountain View, CA US

Patent application number	Description	Published
20100155786	Methods and devices for forming nanostructure monolayers and devices including such monolayers - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.	06-24-2010
20110150695	ELECTRONIC GRADE METAL NANOSTRUCTURES - Methods for producing electronic grade metal nanostructures having low levels of contaminants are provided. Monolayer arrays, populations, and devices including such electronic grade nanostructures are described. In addition, novel methods and compositions for production of Group 10 metal nanostructures and for production of ruthenium nanostructures are provided, along with methods for recovering nanostructures from suspension.	06-23-2011
20110204432	Methods and Devices for Forming Nanostructure Monolayers and Devices Including Such Monolayers - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.	08-25-2011
20110251295	Electronic Grade Metal Nanostructures - Methods for producing electronic grade metal nanostructures having low levels of contaminants are provided. Monolayer arrays, populations, and devices including such electronic grade nanostructures are described. In addition, novel methods and compositions for production of Group 10 metal nanostructures and for production of ruthenium nanostructures are provided, along with methods for recovering nanostructures from suspension.	10-13-2011
20140035011	METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided.	02-06-2014
20140272576	METHODS AND APPARATUS FOR HIGH CAPACITY ANODES FOR LITHIUM BATTERIES - An electrode is provided for an electrochemical lithium battery cell. The electrode includes a bulk material that has a plurality of voids dispersed substantially throughout the bulk material. The bulk material is silicon. Numerous other aspects are provided.	09-18-2014

Sumant Ranganathan, Saratoga, CA US

Patent application number	Description	Published
20110115604	REMOTE CONTROL FOR MULTIMEDIA SYSTEM HAVING TOUCH SENSITIVE PANEL FOR USER ID - Operating a remote control to identify a user by receiving touch pad input from at least one touch sensitive element of the remote control that has a plurality of touch sensitive elements. The touch pad input corresponds to the user's touch of at least some of the plurality of touch sensitive elements. The touch pad input is at least partially processed by processing circuitry of the remote control and transmitted to a multimedia system console via a communications interface of the remote control for processing of the at least partially processed touch pad input to identify the user via pattern recognition. At least partially processing the touch pad input can be by identifying at least one finger orientation, at least one finger spacing, at least one finger width, a plurality of finger knuckle/joint locations, and/or a plurality of finger lengths based upon the touch pad input.	05-19-2011
20110115741	TOUCH SENSITIVE PANEL SUPPORTING STYLUS INPUT - Operating a user input device by scanning touch sensitive elements of a touch pad to measure touch sensitive element values. The touch sensitive element values are compared to a stylus input threshold pattern. Upon a favorable comparison, a stylus input condition is determined, stylus input touch pad processing settings are enacted, and a position of the stylus upon the touch pad is detected. Detection of the stylus position upon the touch pad is based upon the touch sensitive element values and the stylus input touch pad processing settings. The touch sensitive element values are compared to a touching finger threshold pattern. Upon a favorable comparison, a touching finger condition is determined, touching finger touch pad processing settings are enacted, and the touching finger's position upon the touch pad is detected based upon the touch sensitive element values.	05-19-2011
20110118024	ADJUSTING OPERATION OF TOUCH SENSITIVE PANEL OF GAME CONTROLLER - Operating a game controller by setting initial operational parameters of at least one touch sensitive pad of the game controller. The touch sensitive pad has a plurality of touch sensitive elements. Touch pad input is received from the at least one touch sensitive pad of the game controller. The touch pad input corresponds to a user's touch of at least some of the plurality of touch sensitive elements. The touch pad input is at least partially processed by processing circuitry of the game controller and transmitted to a game console via a communications interface of the game controller for processing. Upon meeting an operational parameter alteration condition, the operational parameters of the at least one touch sensitive pad of the game controller are altered.	05-19-2011
20110118025	GAME CONTROLLER WITH TOUCH PAD USER INTERFACE - A game controller with a communications interface, at least one touch sensitive pad having a plurality of touch sensitive elements, and processing circuitry coupled to the communications interface and the at least one touch sensitive pad. The processing circuitry receives touch pad input via the plurality of touch sensitive elements of the at least one touch sensitive pad. The processing circuitry then transmits the touch pad input to a game console via the communications interface. The touch sensitive pad can have a plurality of separate and distinct touch sensitive pads, allowing the processing circuitry to receive touch pad input via each of the plurality of separate and distinct touch sensitive pads. Touch pad input could include user finger and/or user thumb touch pad input.	05-19-2011
20110118026	HAND-HELD GAMING DEVICE THAT IDENTIFIES USER BASED UPON INPUT FROM TOUCH SENSITIVE PANEL - Operating a game controller to identify a user by receiving touch pad input from at least one touch sensitive pad of the game controller that has a plurality of touch sensitive elements. The touch pad input corresponds to the user's touch of at least some of the plurality of touch sensitive elements. The touch pad input is at least partially processed by processing circuitry of the game controller and transmitted to a game console via a communications interface of the game controller for processing of the at least partially processed touch pad input to identify the user via pattern recognition. At least partially processing the touch pad input can be by identifying at least one finger orientation, at least one finger spacing, at least one finger width, a plurality of finger knuckle/joint locations, and/or a plurality of finger lengths based upon the touch pad input.	05-19-2011
20110118028	HAND-HELD GAMING DEVICE WITH CONFIGURABLE TOUCH SENSITIVE PANEL(S) - A game controller with a communications interface, at least one touch sensitive pad having a plurality of touch sensitive elements, and processing circuitry coupled to the communications interface and the at least one touch sensitive pad. The processing circuitry enacts touch pad configuration settings that correlate subsets of the plurality of touch sensitive elements to respective distinct user input locations. The processing circuitry receives touch pad input from the at least one touch sensitive pad. The touch pad input corresponds to a user's touch of at least some of the plurality of touch sensitive elements. The processing circuitry processes the touch pad input to determine user input directions based upon the touch pad configuration settings, and then transmits the touch pad input directions to a game console via the communications interface for use as gaming input.	05-19-2011
20110118029	HAND-HELD GAMING DEVICE WITH TOUCH SENSITIVE PANEL(S) FOR GAMING INPUT - Operating a game controller by receiving touch pad input from at least one touch sensitive pad of the game controller that has a plurality of touch sensitive elements. The touch pad input corresponds to the user's touch of at least some of the plurality of touch sensitive elements. The touch pad input is at least partially processed by processing circuitry of the game controller and the at least partially processed touch pad input is transmitted to a game console via a communications interface of the game controller for use as gaming input. At least partially processing the touch pad input can be by determining hand/foot position, changes in hand/foot position, hand grip/foot pressure, changes in hand grip/foot pressure based upon the touch pad input.	05-19-2011
20110187316	MULTI-VOLTAGE MULTI-BATTERY POWER MANAGEMENT UNIT - A system and method for implementing a multi-voltage multi-battery power management integrated circuit. Various aspects of the present invention provide a power management integrated circuit. The power management IC may comprise a first regulator module that receives a first battery power signal from a first battery characterized by a first battery voltage and outputs a first regulated power signal, based at least in part on the first battery power signal. The power management IC may also comprise a second regulator module that receives a second battery power signal from a second battery characterized by a second battery voltage and outputs a second regulated power signal, based at least in part on the second battery power signal. The second battery voltage may, for example, be substantially different than the first battery voltage. The power first and second regulated power signals may, for example, correspond to substantially different power supply voltages.	08-04-2011
20110193809	Systems and Methods for Providing Enhanced Touch Sensing - Provided are systems and methods for providing enhanced touch sensing. One system providing enhanced touch sensing includes a multi-mode touch screen and a processor configured to apply at least one test signal to a sense element of the multi-mode touch screen, detect at least one return signal from the sense element, and then determine a relative position of an object corresponding to the at least one return signal, the multi-mode touch screen being capable of sensing the first object using first and second detection modes. One multi-mode touch screen comprises a multi-mode multi-touch touch screen. One processor is configured to apply an adaptive test signal to a sense element of a touch screen.	08-11-2011
20120299868	High Noise Immunity and High Spatial Resolution Mutual Capacitive Touch Panel - A mutual capacitive touch panel providing improved noise immunity and improved spatial resolution is described. The touch panel includes a drive line having a plurality of drive electrodes. The touch panel further includes a sense line arranged at an angle with respect to the drive line and the sense line having a plurality of sense electrodes, such that each of the plurality of sense electrodes overlies one of the plurality of drive electrodes. The touch panel is further configured such that a perimeter of each of the plurality of drive electrodes encompasses a perimeter of at least one of the plurality of sense electrodes.	11-29-2012
20130109441	Method of Calibrating the Delay of an Envelope Tracking Signal	05-02-2013
20130176269	HIGHLY CONFIGURABLE ANALOG PREAMP WITH ANALOG TO DIGITAL CONVERTER - A mode-configurable amplifier comprises a single-ended input for receiving a received signal from a capacitive touch panel, a differential output operable to carry a differential processed signal to a subsequent processing stage, and processing circuitry in communication with the single ended input and the differential output. The processing circuitry comprises mode selection inputs and mode selection circuitry in communication with the mode selection inputs. The mode selection circuitry is operable to configure the processing circuitry into a current operating mode selected from a high-pass filter mode, bandpass filter mode, and a trans-capacitive gain mode. The high-pass filter mode is operable to high-pass filter the received signal to obtain the differential processed signal. The bandpass filter mode is operable to bandpass filter the received signal to obtain the differential processed signal. The wideband gain mode is operable to amplify the received signal to obtain the differential processed signal.	07-11-2013
20130176271	ORTHOGONAL MULTI-ROW TOUCH PANEL STIMULATION - Control circuitry for a touch panel includes a touch panel interface, a memory comprising scanning logic, and a controller in communication with the memory and the touch panel interface. The controller is operable, when the scanning logic is executed, to energize a first and a second row in the touch panel simultaneously, a first time; obtain a first signal measurement along a column intersecting the first and second rows; energize the first and the second row in the touch panel simultaneously, a second time; obtain a second signal measurement along the column; and determine a first pixel value and a second pixel value along the column from the first signal measurement and the second signal measurement.	07-11-2013
20130176273	FAST TOUCH DETECTION IN A MUTUAL CAPACITIVE TOUCH SYSTEM - A method for touch detection in a touch panel display includes entering a low power touch detection mode and intermittently stimulating the touch panel display with signals to determine if any touch event occurs without locating the touch event on the touch panel. If a touch event is detected, a full scan mode is entered to locate the touch event on the touch panel. This provides both faster touch detection and lower power operation for the touch panel display and controller circuit.	07-11-2013
20130176274	ASYMMETRIC MULTI-ROW TOUCH PANEL SCANNING - Asymmetric scanning logic implements asymmetric panel scanning by scanning some rows on a touch panel more frequently than other rows. Note that although an entire row at a time may be driven, if only particular pixels in the row are of interest (e.g., included in any region of interest for focused asymmetric scanning), then circuitry may power down the receivers for the columns in which the pixels exist to save power. The asymmetric scanning logic facilitates focused attention to specific areas of interest on the touch panel, to compensate, for example, for high noise or low signal strength in those areas of interest.	07-11-2013
20130176275	HIGH-ACCURACY TOUCH POSITIONING FOR TOUCH PANELS - Control circuitry for a touch panel includes a touch panel interface, a memory comprising touch positioning logic, and a controller in communication with the memory and the touch panel interface. The controller is operable, when the touch positioning logic is executed, to perform selected processing of the touch panel, including scanning a touch panel and determining a touch panel blob resulting from a touch, obtaining blob characteristics of the touch panel blob, and determining a position of the blob relative to the touch panel based on the blob characteristics. The blob characteristics can be adjusted to more accurately position the blob in circumstances where the blob is located near the edge of the touch panel, is in close proximity to another blob, or when the touch panel has variation in the received signal noise.	07-11-2013
20130237322	HAND-HELD GAMING DEVICE WITH CONFIGURABLE TOUCH SENSITIVE PANEL(S) - A game controller with a communications interface includes a touch sensitive pad having a plurality of touch sensitive elements, and processing circuitry coupled to the communications interface and the at least one touch sensitive pad. The processing circuitry enacts touch pad configuration settings that correlate subsets of the plurality of touch sensitive elements to produce distinct user input locations. The processing circuitry receives touch pad input from the at least one touch sensitive pad. The processing circuitry processes the touch pad input to determine user input directions based upon the touch pad configuration settings, and then transmits the touch pad input directions via the communications interface for use as gaming input.	09-12-2013
20130328158	SEMICONDUCTOR SEAL RING DESIGN FOR NOISE ISOLATION - A semiconductor structure includes a substrate layer and a conductive layer connected with the substrate layer. An active circuit is connected with the conductive layer. A seal ring is connected with the conductive layer and separated from the active circuit by an assembly isolation region. An electrical isolation region is positioned in the conductive layer and adjacent to the assembly isolation region, where the electrical isolation region extends to the substrate layer.	12-12-2013
20140125623	BASELINE RECALCULATION AFTER FREQUENCY RECONFIGURATION OF A MUTUAL CAPACITIVE TOUCH CONTROLLER - Systems and methods are provided that allow a touch sensor, such as a mutual capacitive touch panel, to switch from an operative transmit (TX) frequency at which the mutual capacitive touch panel is driven to an alternative TX frequency. When switching to an alternative TX frequency, an alternative baseline capacitance value corresponding to the alternative TX frequency may be utilized to determine whether a touch event has occurred on the mutual capacitive touch panel. Frame scans can be repeatedly performed at the operative TX frequency and the alternative TX frequency in rapid succession, and an average difference of the frame scans can be calculated and utilized to generate the alternative baseline capacitance value which may be insensitive to sudden ambient changes and moving touch events affecting the mutual touch capacitive panel.	05-08-2014
20140176359	REFERENCE CHARGE CANCELLATION FOR ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter (ADC) includes reference charge cancellation features to at least partially offset a voltage distortion on a bypass capacitor of a reference buffer due to a voltage reference hit taken by a switched capacitor bank with which the bypass capacitor is connected. The charge cancellation may be configured in logic to be input signal dependent because different resolved bits or transitions between resolved bits may cause different amounts of voltage reference hits. By adjusting the bypass capacitor in response to each of at least some of the reference hits while resolving a word of bits, the reference voltage signal provided by the bypass capacitor undergoes far less settling, remaining more stable and linear for a more accurate reference voltage. Furthermore, a smaller capacitor may be used for the bypass capacitor, reducing power consumption and area on chip.	06-26-2014
20140210768	Single Layer Touch Sensor - According to an exemplary implementation, a touch sensor includes a plurality of traces situated between first and second columns of transmitter pads on a substrate. Each trace in the plurality of traces is routed from one extremity of the substrate and ends at a corresponding transmitter pad thereby creating an available area between the first and second columns of transmitter pads for one or more remaining traces of the plurality of traces. In some implementations, for at least one trace in the plurality of traces, each of the one or more remaining traces have an expanded width in the available area. Furthermore, at least one dummy pad can be situated in the available area for at least one trace in the plurality of traces.	07-31-2014
20150049052	Wireless Device With Touch-Based Stylus - Often times, a touch-sensitive area of a touch-screen of a communication device is touched by a finger or a hand of a user. In some instances, a touch-based stylus of the present disclosure is available to the user. The user touches the touch-sensitive area of the communication device with the touch-based stylus. The communication device induces a current within the touch-based stylus. This induced current causes a voltage to accumulate within the passive object when touched by the user. This accumulated voltage transfers to the touch-sensitive area when the touch-based stylus touches the touch-sensitive area of the communication device. Thereafter, the communication device compares signal metrics of various regions of the touch-sensitive area to detect an instance and/or a location of the touch from the touch-based stylus.	02-19-2015
20150091869	Orthogonal Multi-Row Touch Panel Stimulation - Control circuitry for a touch panel includes a touch panel interface, a memory comprising scanning logic, and a controller in communication with the memory and the touch panel interface. The controller is operable, when the scanning logic is executed, to energize a first and a second row in the touch panel simultaneously, a first time; obtain a first signal measurement along a column intersecting the first and second rows; energize the first and the second row in the touch panel simultaneously, a second time; obtain a second signal measurement along the column; and determine a first pixel value and a second pixel value along the column from the first signal measurement and the second signal measurement.	04-02-2015
20150138153	SYSTEMS AND METHODS FOR PROVIDING ENHANCED TOUCH SENSING - Provided are systems and methods for providing enhanced touch sensing. One system providing enhanced touch sensing includes a multi-mode touch screen and a processor configured to apply at least one test signal to a sense element of the multi-mode touch screen, detect at least one return signal from the sense element, and then determine a relative position of an object corresponding to the at least one return signal, the multi-mode touch screen being capable of sensing the first object using first and second detection modes. One multi-mode touch screen comprises a multi-mode multi-touch touch screen. One processor is configured to apply an adaptive test signal to a sense element of a touch screen.	05-21-2015
20150227241	BASELINE RECALCULATION AFTER FREQUENCY RECONFIGURATION OF A MUTUAL CAPACITIVE TOUCH CONTROLLER - Systems and methods are provided that allow a touch sensor, such as a mutual capacitive touch panel, to switch from an operative transmit (TX) frequency at which the mutual capacitive touch panel is driven to an alternative TX frequency. When switching to an alternative TX frequency, an alternative baseline capacitance value corresponding to the alternative TX frequency may be utilized to determine whether a touch event has occurred on the mutual capacitive touch panel. Frame scans can be repeatedly performed at the operative TX frequency and the alternative TX frequency in rapid succession, and an average difference of the frame scans can be calculated and utilized to generate the alternative baseline capacitance value which may be insensitive to sudden ambient changes and moving touch events affecting the mutual touch capacitive panel.	08-13-2015
20150242021	High-Accuracy Touch Positioning for Touch Panels - Control circuitry for a touch panel includes a touch panel interface, a memory comprising touch positioning logic, and a controller in communication with the memory and the touch panel interface. The controller is operable, when the touch positioning logic is executed, to perform selected processing of the touch panel, including scanning a touch panel and determining a touch panel blob resulting from a touch, obtaining blob characteristics of the touch panel blob, and determining a position of the blob relative to the touch panel based on the blob characteristics. The blob characteristics can be adjusted to more accurately position the blob in circumstances where the blob is located near the edge of the touch panel, is in close proximity to another blob, or when the touch panel has variation in the received signal noise.	08-27-2015
20150253890	Asymmetric Multi-Row Touch Panel Scanning - Asymmetric scanning logic implements asymmetric panel scanning by scanning some rows on a touch panel more frequently than other rows. Note that although an entire row at a time may be driven, if only particular pixels in the row are of interest (e.g., included in any region of interest for focused asymmetric scanning), then circuitry may power down the receivers for the columns in which the pixels exist to save power. The asymmetric scanning logic facilitates focused attention to specific areas of interest on the touch panel, to compensate, for example, for high noise or low signal strength in those areas of interest.	09-10-2015

Sundararajan Ranganathan, Encinitas, CA US

Patent application number	Description	Published
20140264715	METHODS AND APPARATUS FOR CONGESTION-AWARE BUFFERING USING VOLTAGE ISOLATION PATHWAYS FOR INTEGRATED CIRCUIT DESIGNS WITH MULTI-POWER DOMAINS - A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.	09-18-2014
20140374873	METHODS AND APPARATUS FOR CONGESTION-AWARE BUFFERING USING VOLTAGE ISOLATION PATHWAYS FOR INTEGRATED CIRCUIT DESIGNS WITH MULTI-POWER DOMAINS - A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.	12-25-2014

Thangamani Ranganathan, San Jose, CA US

Patent application number	Description	Published
20100090176	Voltage Switchable Dielectric Material Containing Conductor-On-Conductor Core Shelled Particles - A composition of voltage switchable dielectric (VSD) material that comprises a concentration of core shelled particles that individually comprise a conductor core and a conductor shell, so as to form a conductor-on-conductor core shell particle constituent for the VSD material.	04-15-2010
20100090178	VOLTAGE SWITCHABLE DIELECTRIC MATERIAL CONTAINING CONDUCTIVE CORE SHELLED PARTICLES - A composition of voltage switchable dielectric (VSD) material that comprises a concentration of core shelled particles that individually comprise a conductor core and a shell, the shell of each core shelled particle being (i) multilayered, and/or (ii) heterogeneous.	04-15-2010
20110098408	Deoxybenzoin-based Anti-flammable Polyphosphonate and Poly(arylate-phosphonate) Copolymer Compounds, Compositions and Related Methods of Use - Deoxybenzoin-phosphonate and other copolymer compounds, compositions and related methods.	04-28-2011
20110198544	EMI Voltage Switchable Dielectric Materials Having Nanophase Materials - Various embodiments of the invention disclosed herein provide for adjusting the electrical response of a voltage switchable dielectric material by incorporating one or more nanophase materials. Various aspects provide for a VSDM having improved electrical and/or physical properties. In some cases, a VSDM may have improved (e.g., lower) leakage current at a given voltage. A VSDM may have improved resistance to ESD events, and may have improved resistance to degradation associated with protecting against an ESD event.	08-18-2011
20130102754	DEOXYBENZOIN-DERIVED ANTI-FLAMMABLE POLYMERS - The invention provides novel flame-retardant polymers and materials, their synthesis and use. More particularly, the flame-retardant polymers are deoxybenzoin-derived polymers.	04-25-2013

Vasanth Ranganathan, El Dorado Hills, CA US

Patent application number	Description	Published
20160086374	Constant Buffer Size Multi-Sampled Anti-Aliasing Depth Compression - By packing the depth data in a way that is independent of the number of samples, so that memory bandwidth is the same regardless of the number of samples, higher numbers of samples per pixel may be used without adversely affecting buffer cost. In some embodiments, the number of pixels per clock in a first level depth test may be increased by operating in the pixel domain, whereas previous solutions operated at the sample level.	03-24-2016

Venkatesan N. Ranganathan, San Jose, CA US

Patent application number	Description	Published
20100198855	PROVIDING PARALLEL RESULT STREAMS FOR DATABASE QUERIES - A system and method for providing parallel result streams for database queries is provided. The system includes a network including a client, a server, and a database. The client executes an application and sends a query to the server. In response, the server compiles the query to produce a query plan, executes statements in the query plan and sends parallel result streams to the client.	08-05-2010