Patent application number | Description | Published |
20100080035 | SRAM BASED ONE-TIME-PROGRAMMABLE MEMORY - Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state. | 04-01-2010 |
20100083193 | DESIGN OPTIMIZATION WITH ADAPTIVE BODY BIASING - A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit design, (C) generating an adaptive body biasing mesh and (D) generating a layout of the integrated circuit design based upon a plurality of adaptive body biasing corners. | 04-01-2010 |
20110051304 | DEFECTIVITY-IMMUNE TECHNIQUE OF IMPLEMENTING MIM-BASED DECOUPLING CAPACITORS - An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail. | 03-03-2011 |
20120012896 | Integrated Circuit Cell Architecture Configurable for Memory or Logic Elements - An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other. | 01-19-2012 |
20120175683 | Basic Cell Architecture For Structured ASICs - A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs. | 07-12-2012 |
20120290994 | TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT - A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided. | 11-15-2012 |
20130057338 | POWER CONTROLLER FOR SOC POWER GATING APPLICATIONS - A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. | 03-07-2013 |
20130154109 | METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTERPOSER CAPABLE OF BEING REVERSE BIASED TO ACHIEVE REDUCED CAPACITANCE - The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage. | 06-20-2013 |
20130166930 | REDUCING POWER CONSUMPTION OF MEMORY - Described embodiments provide for a memory system adapted to enable power-gating in one or more memories. Each memory has a corresponding timing characteristic. A monitor in the memory system determines a timing threshold and determines whether the timing characteristic of a memory is at least equal to the timing threshold. If the corresponding timing characteristic is at least equal to the timing threshold, power-gating is applied to the memory. | 06-27-2013 |
20130166931 | REDUCING POWER CONSUMPTION OF MEMORY - Described embodiments provide for a memory system which power-gates a memory operating at a first clock. Control logic in the memory system activates, during a rising edge of a second clock, the memory from a sleep mode. The memory is accessed. After a cycle of the first clock, the control logic asserts a power-gating signal, thereby returning the memory to the sleep mode. The frequency of the second clock is less than a frequency of the first clock. | 06-27-2013 |
20140028364 | CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTIVE VOLTAGE SCALING AND METHOD OF OPERATION THEREOF - A critical path monitor (CPM), a method of setting supply voltage based on output of a CPM and an integrated circuit (IC) incorporating the CPM. In one embodiment, the CPM includes: (1) an edge detector configured to produce a thermometer output over a plurality of clock cycles and (2) a min_max recorder, coupled to the edge detector and configured to record minimum and maximum values of the thermometer output during a polling interval. | 01-30-2014 |
20140040842 | TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT - A method of reducing total power dissipation for logic cells using Boolean equations includes selecting a path, identifying at least one group of logic cells for analysis in the path, and deriving Boolean equations for the at least one group of logic cells. Additionally, the method includes listing possible logic cell implementations for each Boolean equation while maintaining original transistor values, verifying path timing for the possible logic cell implementations to provide retained logic cells that achieve a path timing requirement, computing a total power dissipation for the retained logic cells, and choosing a logic cell set from the retained logic cells corresponding to a minimum total power dissipation for the path. A method for reducing total power dissipation for logic cell sets and a processor configured to reduce total power dissipation for groups of logic cells are also provided. | 02-06-2014 |