Patent application number | Description | Published |
20090037614 | Offloading input/output (I/O) virtualization operations to a processor - In one embodiment, the present invention includes a method for receiving a request for a direct memory access (DMA) operation in an input/output (I/O) hub, where the request includes a device virtual address (DVA) associated with the DMA operation, determining in the I/O hub whether to perform an address translation to translate the DVA into a physical address (PA), and sending the request with the DVA from the I/O hub to a processor coupled to the I/O hub if the I/O hub determines not to perform the address translation. Other embodiments are described and claimed. | 02-05-2009 |
20090037624 | Cache coherent switch device - In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed. | 02-05-2009 |
20100169673 | Efficient remapping engine utilization - A device, system, and method are disclosed. In one embodiment device includes remapping engine reallocation logic that is capable of monitoring a first amount of traffic that is translated by a first remapping engine. If the first amount of traffic reaches the threshold level of the first remapping engine, then the logic will divert a portion of the traffic to be translated by a second remapping engine. | 07-01-2010 |
20100205380 | Cache Coherent Switch Device - In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed. | 08-12-2010 |
20110153956 | Cache Coherent Switch Device - In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed. | 06-23-2011 |
20110252168 | Handling Atomic Operations For A Non-Coherent Device - In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed. | 10-13-2011 |
20110302425 | SYSTEMS, METHODS, AND APPARATUS TO VIRTUALIZE TPM ACCESSES - Embodiments of system, method, and apparatus for virtualizing TPM accesses is described. In some embodiments, an apparatus including a CPU core to execute a software program, a manageability engine coupled to the CPU core, the manageability engine to receive a trusted platform module (TPM) command requested by the software program and to process the TPM command utilizing a manageability firmware by at least creating a TPM network packet, and a network interface coupled to the manageability engine to transmit the TPM network packet to a remote TPM that is external to the apparatus for processing is utilized as a part of this virtualization process. | 12-08-2011 |
20120331227 | FACILITATING IMPLEMENTATION, AT LEAST IN PART, OF AT LEAST ONE CACHE MANAGEMENT POLICY - An embodiment may include circuitry to facilitate implementation, at least in part, of at least one cache management policy. The at least one policy may be based, at least in part, upon respective priorities of respective classifications of respective network traffic. The at least one policy may concern, at least in part, caching of respective information associated, at least in part, with the respective network traffic belonging to the respective classifications. Many alternatives, variations, and modifications are possible. | 12-27-2012 |
20130007768 | Atomic operations on multi-socket platforms - Methods and apparatus relating to atomic operations on multi-socket/multi-processor platforms are described. In one embodiment, a first agent (such as a processor core) is coupled to a second agent (such as an input/output device) via a link. A memory, coupled to the first agent, stores a device driver, corresponding to the second agent, and an operating system (OS) for the first agent. The OS detects an affinity mask that indicates which agents are to be quiesced for an atomic operation to be issued by the second agent. The agents identified by the affinity mask are then quiesced in response to receipt of the atomic operation from the second agent. Other embodiments are also disclosed and claimed. | 01-03-2013 |
20130080667 | Handling Atomic Operations For A Non-Coherent Device - In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed. | 03-28-2013 |
20130298250 | Systems, Methods, and Apparatus to Virtualize TPM Accesses - Embodiments of system, method, and apparatus for virtualizing TPM accesses is described. In some embodiments, an apparatus including a CPU core to execute a software program, a manageability engine coupled to the CPU core, the manageability engine to receive a trusted platform module (TPM) command requested by the software program and to process the TPM command utilizing a manageability firmware by at least creating a TPM network packet, and a network interface coupled to the manageability engine to transmit the TPM network packet to a remote TPM that is external to the apparatus for processing is utilized as a part of this virtualization process. | 11-07-2013 |
20140089533 | ALLOCATION OF FLOW CONTROL CREDITS FOR HIGH PERFORMANCE DEVICES - Methods and apparatus relating to allocation of flow control credits for high performance devices are described. In some embodiments, controls and/or configuration structures may be provided for the OS (Operating System) or VMM (Virtual Machine Manager) to indicate possible processor affinity (e.g., of a device driver for a given PCIe device) to the platform components (in a platform dependent fashion, for example). Using this data, the platform components could configure the RC (Root Complex) ports and/or intermediate components (such as switches, bridges, etc.) to pre-allocate buffers for the links coupling the PCIe device to the RC ports or intermediate components. Other embodiments are also disclosed and claimed. | 03-27-2014 |
20140250250 | Power-Optimized Interrupt Delivery - An apparatus, method, system, and computer-readable medium are disclosed. In one embodiment the apparatus is a processor. The processor includes thread remapping logic that is capable of tracking hardware thread interrupt equivalence information for a first hardware thread and a second hardware thread. The processor also includes logic to receive an interrupt issued from a device, wherein the interrupt has an affinity tied to the first hardware thread. The processor also includes logic to redirect the interrupt to the second hardware thread when the hardware thread interrupt equivalence information validates the second hardware thread is capable of handling the interrupt. | 09-04-2014 |
20150032924 | Handling Atomic Operations For A Non-Coherent Device - In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed. | 01-29-2015 |