Patent application number | Description | Published |
20090302421 | Method and apparatus for creating a deep trench capacitor to improve device performance - A deep trench capacitor includes a trench having walls and a floor. The deep trench capacitor also includes a layer of gate oxide on the walls and floor. Gate polysilicon is deposited over the gate oxide. | 12-10-2009 |
20100148304 | INTEGRATED CIRCUIT DECOUPLING CAPACITORS - Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect. | 06-17-2010 |
20130002287 | APPARATUS FOR IMPROVING RELIABILITY OF ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS - In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus. | 01-03-2013 |
20130043536 | BUFFERED FINFET DEVICE - One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed. | 02-21-2013 |
20130043902 | APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRAYS AND ASSOCIATED METHODS - A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values. | 02-21-2013 |
20130127494 | MEMORY ELEMENTS WITH RELAY DEVICES - Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity. | 05-23-2013 |
20140085967 | MEMORY ELEMENTS WITH RELAY DEVICES - Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity. | 03-27-2014 |
Patent application number | Description | Published |
20090245246 | SYSTEMS AND METHODS FOR IMPROVING PACKET SCHEDULING ACCURACY - A packet scheduler is configured to perform quality of service (QoS) scheduling on a per-data unit basis. A downstream processing engine is operatively connected to the packet scheduler for receiving forwarded packets. A feedback path is operatively connected between the downstream processing engine and the packet scheduler for transmitting a net data unit change value reflecting a change in packet size between an output of the packet scheduler and an output of the downstream processing engine. | 10-01-2009 |
20100290342 | HIERARCHICAL POLICERS FOR ENFORCING DIFFERENTIATED TRAFFIC BEHAVIOR - A hierarchical traffic policer may include a first policer configured to pass first packets when a first condition is met. The first policer also may alter selection information within the passed first packets. A second policer may be configured to pass second packets when a second condition is met. The second policer may be further configured to pass all of the passed first packets from the first policer based on the altered selection information within the passed first packets. | 11-18-2010 |
20110228784 | REORDER ENGINE WITH ERROR RECOVERY - A reorder engine classifies information relating to incoming data items as belonging to either a first, second, or third region. The information relating to the data items may arrive at the reorder engine out of order. The data items each include a sequence number through which the reorder engine may reconstruct the correct order of the data items. Based on the classification, the reorder engine may either process the data items normally or drop certain ones of the data items. The majority of incoming data items will fall in the first region and are processed normally. Data items arriving in the second region indicate that a previous data item is late or delayed. If this previous data item is delayed but does eventually arrive, it will arrive in the third region and is simply ignored. | 09-22-2011 |
20120087374 | CONTEXT-SWITCHED MULTI-STREAM PIPELINED REORDER ENGINE - A pipelined reorder engine reorders data items received over a network on a per-source basis. Context memories correspond to each of the possible sources. The pipeline includes a plurality of pipeline stages that together simultaneously operate on the data items. The context memories are operatively coupled to the pipeline stages and store information relating to a state of reordering for each of the sources. The pipeline stages read from and update the context memories based on the source of the data item being processed. | 04-12-2012 |
20150052316 | CENTRALIZED MEMORY ALLOCATION WITH WRITE POINTER DRIFT CORRECTION - A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range. | 02-19-2015 |
Patent application number | Description | Published |
20150242859 | METHOD AND SYSTEM FOR USE OF BIOMETRIC INFORMATION ASSOCIATED WITH CONSUMER INTERACTIONS - Embodiments provide a computer-executed method, a computer system and computer program product for facilitating a commercial transaction. The method includes transmitting computer-executable instructions to cause a representation of an item to be displayed on a consumer interface rendered on a visual display of a computing device associated with a consumer. The method also includes receiving, from the computing device, an indication of consumer input performed using the consumer interface, the consumer input associated with the representation of the item available for a commercial transaction. The method also includes receiving, from the computing device, biometric information associated with the consumer. The method also includes determining an identity of the consumer based on the biometric information and, based on the identity of the consumer, associating the consumer input with a predetermined command defined for the consumer. The method further includes transmitting computer-executable instructions to facilitate a transaction associated with the command with respect to the item. | 08-27-2015 |
20150242902 | METHOD AND SYSTEM FOR FACILITATING CONSUMER INTERACTIONS WITH PROMOTIONS - Embodiments provide a computer-executed method, a computer system and non-transitory computer-readable media for facilitating consumer interaction with a promotion. The method includes transmitting computer-executable instructions to cause an impression of a promotion to be displayed on a consumer interface rendered on a visual display of a computing device. The method also includes receiving, from the computing device, an indication of a compound consumer input associated with a consumer and performed using the consumer interface. The method also includes determining that the compound consumer input corresponds to a command for performing an action associated with the promotion. The method further includes, based on a determination that the compound consumer input corresponds to the command, transmitting computer-executable instructions to initiate execution of the command associated with the promotion. | 08-27-2015 |
20150242937 | METHOD AND SYSTEM FOR A PREDEFINED SUITE OF CONSUMER INTERACTIONS FOR INITIATING EXECUTION OF COMMANDS - Embodiments provide a computer-executed method, a computer system and non-transitory computer-readable media for facilitating consumer interaction with a consumer interface. The method includes displaying a representation of an item on a consumer interface rendered on a visual display of a computing device. The method also includes storing, on a non-transitory computer-readable medium: a predefined first association between a first compound consumer input and a first command such that receipt of the first compound consumer input at the consumer interface initiates the first command, and a predefined second association between a second compound consumer input and a second command such that receipt of the second compound consumer input at the consumer interface initiates the second command. The method further includes, upon detection of the first compound consumer input entered at the consumer interface, initiating execution of the first command in relation to the item; and, upon detection of the second compound consumer input entered at the consumer interface, initiating execution of the second command in relation to the item. | 08-27-2015 |
20150242938 | METHOD AND SYSTEM FOR DEFINING CONSUMER INTERACTIONS FOR INITIATING EXECUTION OF COMMANDS - Embodiments provide a computer-executed method, a computer system and computer program product for initiating a command. The method includes causing a consumer input definition interface to be displayed on a visual display of a computing device associated with a consumer, wherein the consumer input definition interface includes an indication of a command. The method also includes, while the consumer input definition interface is displayed, receiving input definition data defining a consumer interaction by the consumer. The method also includes generating a compound consumer input based on the input definition data, and associating the compound consumer input with the command and the consumer. The method further includes storing the association between the compound consumer input and the command on a non-transitory storage device so that receipt of the compound consumer input from the consumer automatically initiates the command. | 08-27-2015 |
20150242941 | METHOD AND SYSTEM FOR FACILITATING CONSUMER INTERACTIONS FOR PERFORMING PURCHASE COMMANDS - Embodiments provide a computer-executed method, a computer system and computer-program product for facilitating a transaction. The method includes transmitting computer-executable instructions to cause a representation of an item to be displayed on a consumer interface rendered on a visual display of a computing device. The method also includes receiving, from the computing device, an indication of a compound consumer input associated with a consumer and performed using the consumer interface. The method further includes, based on a determination that the compound consumer input corresponds to a purchase command, retrieving information previously stored for the consumer, generating an order to purchase the item for the consumer, and transmitting an order confirmation configured to be displayed by the computing device. | 08-27-2015 |
20150242942 | METHOD AND SYSTEM FOR ADJUSTING ITEM RELEVANCE BASED ON CONSUMER INTERACTIONS - Embodiments provide a computer-executed method, a computing device, and computer program product for enabling indication of a relevance of an item. The method includes displaying a consumer interface on a visual display of a computing device associated with a consumer, the consumer interface rendering representations of one or more items. The method also includes receiving, at the computing device, an indication of consumer input with respect to at least one of the items. The method also includes, based on a determination that the consumer input corresponds to a relevance command, adjusting the display of the representations of the one or more items on the consumer interface. The method further includes, based on the relevance command, determining a relevance indication of a characteristic of the at least one item to the consumer. | 08-27-2015 |
Patent application number | Description | Published |
20080201671 | METHOD FOR GENERATING TIMING EXCEPTIONS - A method for generating timing exceptions for integrated circuit (IC) designs is disclosed. The method includes synthesizing an input RTL description into a gate-level netlist mapped to a technology library; detecting timing critical paths in the netlist; and determining for each detected timing critical path whether it induces timing exceptions. The timing exceptions generated by the disclosed method include, but are not limited to, multi-cycle paths, clock domain crossing false paths, asynchronous false paths, functional false paths, combinational false paths, sequential false paths, timing false paths, and the like. | 08-21-2008 |
20080288904 | METHOD FOR MODELING AND VERIFYING TIMING EXCEPTIONS - A method and system for timing exception verification in integrated circuit (IC) designs included verification of functional false paths as well as multi-cycle paths (MCPs). A false path or a MCP is modeled to a satisfiability formula and the formula is validated using a Boolean satisfiability solver. Time required for timing exception verification can be significantly reduced. | 11-20-2008 |
20110288825 | METHOD AND SYSTEM FOR EQUIVALENCE CHECKING - As part of the design process it is required to design circuits in order to reduce their power consumption. This is typically done by enabling or disabling flip-flops (FFs), however, such change in the circuit requires certain verification. As sequential clock gating changes the state function it is necessary to perform a sequential equivalence checking (SEC) verification. Applying a full SEC may be runtime consuming and is not scalable for large designs. Methods to reduce the problem of verifying sequential clock gating by reducing the sequential problem into much smaller problem that can be easily solved is therefore shown. | 11-24-2011 |