| Patent application number | Description | Published |
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| 20120067397 | SYSTEM AND METHOD FOR DETERMINING PLACEMENT OF PHOTOVOLTAIC STRIPS USING DISPLACEMENT SENSORS - A method for forming a solar energy collection device includes receiving a sheet of glass comprising glass material, wherein the sheet of glass includes a plurality of light concentrating geometric features, measuring geometric characteristics for the plurality of light concentrating geometric features, mathematically calculating predicted light concentration characteristics for each of the plurality of light concentrating geometric features in response to the geometric characteristics, determining placement locations for a plurality of PV strips in response to the predicted light concentration characteristics for each of the plurality of light concentrating geometric features, and securing the plurality of PV strips relative to the sheet of glass in response to the placement locations for the plurality of PV strips. | 03-22-2012 |
| 20120067398 | SYSTEM AND METHOD FOR LAMINATING PHOTOVOLTAIC STRUCTURES - A method for forming a laminated photovoltaic structure includes providing a sheet of transparent material having light concentrating features, disposing adhesive material adjacent to the sheet of transparent material, disposing photovoltaic strips adjacent to the adhesive material, wherein the photovoltaic strips are positioned relative to the sheet of transparent material in response to exitant light characteristics of the light concentrating features, wherein photovoltaic strips are coupled via associated bus bars, wherein gap regions are located between bus bars of neighboring photovoltaic strips, disposing a rigid layer of material adjacent to the photovoltaic strips to form a composite photovoltaic structure; and thereafter laminating the composite photovoltaic structure to fill the gap regions with adhesive material and to form the laminated photovoltaic structure, wherein adhesive material adheres to the bus bars. | 03-22-2012 |
| 20120167948 | SYSTEM AND METHOD FOR FORMING PHOTOVOLTAIC MODULES - A method for forming a solar energy collection device includes determining physical concentration characteristics for a plurality of light concentrating geometric features of a sheet of transparent material, determining placements for a plurality of photovoltaic strips in response to the physical concentration characteristics for the plurality of light concentrating geometric features, wherein the placements for each of the plurality of photovoltaic strips is associated with a two-dimensional displacement and an offset angle, placing the plurality of photovoltaic strips onto a stage in response to two-dimensional displacements and offset angles associated with each of the plurality of photovoltaic strips, and electrically coupling the plurality of photovoltaic strips with a plurality of conductors to form a photovoltaic assembly. | 07-05-2012 |
| 20120211052 | PHOTOVOLTAIC STRIP SOLAR MODULES AND METHODS - A light energy collection device includes a glass layer having light concentrators for receiving light and for concentrating concentrated light, the light concentrators are elongated and substantially parallel manner to a first edge of the glass layer, wherein pitches of the light concentrators vary along the length generally within the range of approximately 5.5-5.8 mm, strings of multiple PV strips extending in a parallel manner to a second edge (perpendicular to the first edge) of the glass layer, wherein a string of PV strips includes: electrodes extending substantially parallel to the second edge, PV strips electrically coupled to the electrodes and extending substantially parallel to the first edge, wherein pitches of the PV strips vary along their length according to varying pitches of the light concentrators, wherein the PV strips receive concentrated light and output electrical energy in response to the concentrated light. | 08-23-2012 |
| 20130206208 | SYSTEM AND METHOD FOR DETERMINING PLACEMENT OF PHOTOVOLTAIC STRIPS USING DISPLACEMENT SENSORS - A method for forming a solar energy collection device includes receiving a sheet of glass comprising glass material, wherein the sheet of glass includes a plurality of light concentrating geometric features, measuring geometric characteristics for the plurality of light concentrating geometric features, mathematically calculating predicted light concentration characteristics for each of the plurality of light concentrating geometric features in response to the geometric characteristics, determining placement locations for a plurality of PV strips in response to the predicted light concentration characteristics for each of the plurality of light concentrating geometric features, and securing the plurality of PV strips relative to the sheet of glass in response to the placement locations for the plurality of PV strips. | 08-15-2013 |
| 20130214432 | STACKED DIE ASSEMBLY - Embodiments of stacked die assemblies for an IC are disclosed. One embodiment includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer. | 08-22-2013 |
| Patent application number | Description | Published |
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| 20140330891 | VIRTUAL DESKTOP ACCELERATOR WITH SUPPORT FOR DYNAMIC PROXY THREAD MANAGEMENT - In particular embodiments, a method includes determining a data flow rate of the active connections at a proxy, comparing the data flow rate to a first pre-determined threshold value, and, when the data flow rate exceeds the first pre-determined threshold value, creating one or more new processing threads associated with the proxy. | 11-06-2014 |
| 20140331046 | VIRTUAL DESKTOP ACCELERATOR WITH SUPPORT FOR MULTIPLE CRYPTOGRAPHIC CONTEXTS - In particular embodiments, a method includes intercepting a remote desktop connection request and connecting to a network gateway based on the remote desktop connection request. A first connection with a server is initiated via the network gateway using a first communication protocol. A plurality of cryptographic contexts are exchanged with the server. A token encrypted using one of the plurality of cryptographic contexts is received from the server. The token is sent from a client device to the server or a proxy to authenticate the client device, and a second connection is initiated with the server, via the proxy, using a second communication protocol. | 11-06-2014 |
| 20140331054 | VIRTUAL DESKTOP ACCELERATOR WITH ENHANCED BANDWIDTH USAGE - In particular embodiments, a method includes receiving a request for a signature verification. In response to the request, signature data is encrypted. A first data size associated with the signature data is determined. A second data size associated with data of a data packet is determined. The method includes comparing the sum of the first data size and the second data size to a pre-determined data size. When the sum is less than or equal to the pre-determined data size, the encrypted signature data is included in the data packet; and the data packet is transmitted over a network. | 11-06-2014 |
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| 20140068284 | Configuring Power Management Functionality In A Processor - In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed. | 03-06-2014 |
| 20140068290 | Configuring Power Management Functionality In A Processor - In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed. | 03-06-2014 |
| 20150089173 | SECURE MEMORY REPARTITIONING - Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section are convertible in response to a section conversion instruction. | 03-26-2015 |
| 20150100796 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-09-2015 |
| 20150100797 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-09-2015 |
| 20150100798 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-09-2015 |
| 20150104007 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-16-2015 |
| 20150104008 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-16-2015 |
| 20150104009 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-16-2015 |
| 20150104010 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-16-2015 |
| 20150154122 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 06-04-2015 |
| 20150178226 | USING AUTHENTICATED MANIFESTS TO ENABLE EXTERNAL CERTIFICATION OF MULTI-PROCESSOR PLATFORMS - Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a plurality of processing devices communicatively coupled to the architecturally protected memory, each processing device comprising a first processing logic to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory, or preventing an unauthorized access to the architecturally protected memory; wherein each processing device further comprises a second processing logic to establish a secure communication channel with a second processing device of the processing system, employ the secure communication channel to synchronize a platform identity key representing the processing system, and transmit a platform manifest comprising the platform identity key to a certification system. | 06-25-2015 |
| 20160085293 | Configuring Power Management Functionality In A Processor - In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed. | 03-24-2016 |
| 20160119123 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
| 20160119124 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
| 20160119125 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
| 20160119126 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
| 20160119127 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
| 20160119128 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
| 20160119129 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
| 20160119130 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
| 20160119131 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
