Patent application number | Description | Published |
20080222340 | Bus Interface Controller For Cost-Effective HIgh Performance Graphics System With Two or More Graphics Processing Units - A bus interface controller manages a set of serial data lanes. The bus interface controller supports operating a subset of the serial data lanes as a private bus. | 09-11-2008 |
20090129163 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INCREASING A LIFETIME OF A PLURALITY OF BLOCKS OF MEMORY - A system, method, and computer program product are provided for increasing a lifetime of a plurality of blocks of memory. In operation, at least one factor that affects a lifetime of a plurality of blocks of memory is identified. Additionally, the plurality of blocks to write is selected, based on the at least one factor. | 05-21-2009 |
20090132778 | SYSTEM, METHOD AND A COMPUTER PROGRAM PRODUCT FOR WRITING DATA TO DIFFERENT STORAGE DEVICES BASED ON WRITE FREQUENCY - A system, method, and computer program product are provided for writing data to different storage devices based on write frequency. In operation, a frequency in which data is written is identified. Additionally, a plurality of storage devices of different types is selected from to write the data, based on the frequency. | 05-21-2009 |
20090138671 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INCREASING SPARE SPACE IN MEMORY TO EXTEND A LIFETIME OF THE MEMORY - A system, method, and computer program product are provided for extending a lifetime of memory. In operation, spare space in memory is increased. Additionally, a lifetime of the memory is extended, as a result of increasing the spare space in the memory. | 05-28-2009 |
20100017566 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INTERFACING COMPUTING DEVICE HARDWARE OF A COMPUTING DEVICE AND AN OPERATING SYSTEM UTILIZING A VIRTUALIZATION LAYER - A system, method, and computer program product are provided for interfacing computing device hardware of a computing device and an operating system. A portable memory device adapted for removable communication with a computing device including computing device hardware is provided. The portable memory device includes an operating system, and a virtualization layer for interfacing the computing device hardware of the computing device and the operating system. | 01-21-2010 |
20100017588 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROVIDING AN EXTENDED CAPABILITY TO A SYSTEM - A system, method, and computer program product are included for providing an extended capability to a system. In operation, a request to boot a system is identified. Additionally, in response to the request, extended capability code is returned. Furthermore, the extended capability code is capable of being executed to provide an extended capability. | 01-21-2010 |
20100017807 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TRANSPARENT COMMUNICATION BETWEEN A STORAGE DEVICE AND AN APPLICATION - A system, method, and computer program product are provided for modulating a response time of a response to an application for communicating with the application. In operation, data from an application is received. Additionally, the application is identified based on the data. Further, a response time of a response to the application is modulated for communicating with the application. | 01-21-2010 |
20100064093 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONVERTING DATA IN A BINARY REPRESENTATION TO A NON-POWER OF TWO REPRESENTATION - A system, method, and computer program product are provided for converting data in a binary representation to a non-power of two representation. In operation, data in a binary representation is identified. Additionally, the data in the binary representation is converted to a non-power of two representation having a non-power of two number of voltage levels. | 03-11-2010 |
20100146236 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR RENDERING AT LEAST A PORTION OF DATA USELESS IN IMMEDIATE RESPONSE TO A DELETE COMMAND - A system, method, and computer program product are provided for rendering at least a portion of data useless in immediate response to a delete command. In operation, a delete command directed to an operating system is received for deleting data from memory. Furthermore, in immediate response to the delete command, a process is initiated for rendering at least a portion of the data useless. | 06-10-2010 |
20100325187 | EFFICIENT MATRIX MULTIPLICATION ON A PARALLEL PROCESSING DEVICE - The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs to result tiles. Yet other embodiments are methods for mapping the individual threads of a CTA to the elements of a tile for result tile computations, source tile copy operations, and source tile copy and transpose operations. The present invention advantageously enables result matrix elements to be computed on a tile-by-tile basis using multiple CTAs executing concurrently on different streaming multiprocessors, enables source tiles to be copied to local memory to reduce the number accesses from the global memory when computing a result tile, and enables coalesced read operations from the global memory as well as write operations to the local memory without bank conflicts. | 12-23-2010 |
20110004710 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INTERFACING ONE OR MORE STORAGE DEVICES WITH A PLURALITY OF BRIDGE CHIPS - A system, method, and computer program product are provided for interfacing one or more storage devices with a plurality of bridge chips. One or more storage devices are provided. Additionally, a plurality of bridge chips are provided. Furthermore, at least one multiplexing device is provided for interfacing the one or more storage devices with the plurality of bridge chips. | 01-06-2011 |
20110125956 | TECHNIQUES FOR MULTI-MEMORY DEVICE LIFETIME MANAGEMENT - Techniques are provided for identifying at least one aspect associated with a lifetime of each of a plurality of memory devices. Further, data is moved between the plurality of memory devices, based on the at least one aspect. | 05-26-2011 |
20110167199 | TECHNIQUES FOR PROLONGING A LIFETIME OF MEMORY BY CONTROLLING OPERATIONS THAT AFFECT THE LIFETIME OF THE MEMORY - Techniques are provided for prolonging a lifetime of memory by controlling operations that affect the lifetime of the memory. At least one aspect associated with the memory lifetime is identified and at least one of the operations is delayed, based on the at least one aspect. The operations include a write operation, an erase operation, a program operation, and/or any other operation that is capable of reducing the memory lifetime. | 07-07-2011 |
20110276745 | TECHNIQUES FOR WRITING DATA TO DIFFERENT PORTIONS OF STORAGE DEVICES BASED ON WRITE FREQUENCY - Techniques for writing data to different portions of storage devices based on write frequencies are disclosed. Frequencies of data writes to various portions of a memory are monitored. The memory includes various storage technologies. Each portion includes one of the storage technologies and has a respective lifetime. An order that the portions are written into and recycled is dynamically managed to equalize respective life expectancies of the portions in view of differences in endurance values of the portions, the monitored frequencies of data writes, and the lifetimes. In some embodiments, the storage technologies include Single-Level Cell (SLC) flash memory storage technology and Multi-Level Cell (MLC) flash memory storage technology. The SLC and MLC flash memory storage technologies are optionally integrated in one device. In some embodiments, the storage technologies include two or more different types of SLC flash memory storage technologies, optionally integrated in one device. | 11-10-2011 |
20120060001 | MEMORY LIFETIME GAUGING SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT - Techniques are taught for reducing writes, and estimating and displaying estimated remaining lifetime of non-volatile memories. The write reducing is optionally via determining a difference between write operation results and data stored in the non-volatile memories. The estimated remaining lifetime is optionally based at least in part on a previous lifetime. The displaying is optionally via a gauge. | 03-08-2012 |
20120060002 | SYSTEM AND METHOD FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES - A storage subsystem receives writes from a computer via a standard storage subsystem interface. The storage subsystem reduces a number of the writes. A single drive of the storage subsystem has primary and redundant storage devices with storage device interfaces. A disk controller of the single drive implements a data redundancy scheme by storing data associated with the reduced number of writes in the primary storage devices and by storing computed redundancy information in the redundant storage devices. The disk controller is operable without a loss of data in the presence of at least a single failure of any of the storage devices. Optionally the storage devices are flash memory devices. Optionally the disk controller is operable without a loss of data in the presence of at least two failures of any of the storage devices when a number of the redundant storage devices is at least two. | 03-08-2012 |
20120060060 | Techiniques increasing a lifetime of blocks of memory - Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized. | 03-08-2012 |
20120124277 | SYSTEM AND METHOD FOR INCREASING CAPACITY, PERFORMANCE, AND FLEXIBILITY OF FLASH STORAGE - In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled. | 05-17-2012 |
20120311378 | Techniques for increasing a lifetime of blocks of memory - Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized. | 12-06-2012 |
20130132645 | SYSTEM AND METHOD FOR INCREASING CAPACITY, PERFORMANCE, AND FLEXIBILITY OF FLASH STORAGE - In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled. | 05-23-2013 |
20130139035 | LDPC Erasure Decoding for Flash Memories - A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria. | 05-30-2013 |
20130212322 | TECHNIQUES FOR REDUCING MEMORY WRITE OPERATIONS USING COALESCING MEMORY BUFFERS AND DIFFERENCE INFORMATION - Techniques are described for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information is stored in coalescing memory buffers. To this end, the write operations may be reduced, utilizing the difference information. | 08-15-2013 |
20130304976 | TECHNIQUES FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES - A storage subsystem receives writes from a computer via a storage subsystem interface. The storage subsystem reduces a number of the writes. A single drive of the storage subsystem has primary and redundant storage devices with storage device interfaces. A disk controller of the single drive implements a data redundancy scheme by storing data associated with the reduced number of writes in the primary storage devices and by storing computed redundancy information in the redundant storage devices. The disk controller is operable without a loss of data in the presence of at least a single failure of any of the storage devices. Optionally the storage devices are flash memory devices. Optionally the disk controller is operable without a loss of data in the presence of at least two failures of any of the storage devices when a number of the redundant storage devices is at least two. | 11-14-2013 |
20130326130 | Techniques for increasing a lifetime of blocks of memory - Techniques are described for increasing a lifetime of a plurality of blocks of memory by equalizing a variation between the blocks. In operation, blocks to be written are allocated from a set of blocks having a lifetime factor below a threshold. The threshold is reset as required to resupply the set of blocks available for allocation. | 12-05-2013 |
20140063721 | CHASSIS WITH SEPARATE THERMAL CHAMBER FOR SOLID STATE MEMORY - A chassis for a network storage system contains a first thermal chamber that houses conventional electronic components and a second thermal chamber that houses non-volatile solid state memory such as flash memory. A cooling system keeps the electronics in first thermal chamber below their maximum junction temperature. Meanwhile, a temperature regulating system maintains the solid state memory in the second thermal chamber within a range of a preferred operating temperature selected to extend the lifetime and/or improve the reliability of the solid state memory. Thus, the chassis provides dual zone temperature control to improve performance of the network storage system. | 03-06-2014 |
20140063722 | MOTHERBOARD WITH CARD GUIDE CUTOUTS - A system for mounting a flash blade in a storage system includes a motherboard with a series of card guide cutouts for aligning flash blades. A flash blade can be aligned perpendicular to the motherboard and aligned parallel to adjacent flash blades by inserting the flash blade into one of the card guide cutouts and connecting the flash blade to a connector at one end of the cutout. This beneficially aligns the flash blade while making efficient use of the available vertical space within a chassis. The flash blade can also extend through the cutout to the other side of the motherboard. The efficient use of vertical space enables an increase in the number of solid state memory can be added to the flash blade relative to conventional designs, thereby improving capacity. | 03-06-2014 |
20140067984 | Integrated Storage and Switching for Memory Systems - An integrated networked storage and switching apparatus comprises one or more flash memory controllers, a system controller, and a network switch integrated within a common chassis. The integration of storage and switching enables the components to share a common power supply and temperature regulation system, achieving efficient use of available space and power, and eliminating added complexity of external cables between the switch a storage devices. Additionally, the architecture enables substantial flexibility and optimization of network traffic policies for both network and storage-related traffic. | 03-06-2014 |
20140101369 | METHODS, DEVICES AND SYSTEMS FOR PHYSICAL-TO-LOGICAL MAPPING IN SOLID STATE DRIVES - A data storage device comprises a plurality of non-volatile memory devices storing physical pages, each stored at a predetermined physical location. A controller may be coupled to the memory devices and configured to access data stored in a plurality of logical pages (L-Pages), each associated with an L-Page number that enables the controller to logically reference data stored in the physical pages. A volatile memory may comprise a logical-to-physical address translation map that enables the controller to determine a physical location, within the physical pages, of data stored in each L-Page. The controller may be configured to maintain, in the memory devices, journals defining physical-to-logical correspondences, each journal covering a predetermined range of physical pages and comprising a plurality of entries that associate one or more physical pages to each L-Page. The controller may read the journals upon startup and rebuild the address translation map from the read journals. | 04-10-2014 |
20140133220 | METHODS AND DEVICES FOR AVOIDING LOWER PAGE CORRUPTION IN DATA STORAGE DEVICES - A data storage device may comprise a plurality of Multi-Level Cell (MLC) non-volatile memory devices comprising a plurality of lower pages and a corresponding plurality of higher-order pages. A controller may be configured to write data to and read data from the plurality of lower pages and the corresponding plurality of higher-order pages. A buffer may be coupled to the controller, which may be configured to accumulate data to be written to the MLC non-volatile memory devices, allocate space in the buffer and write the accumulated data to the allocated space. At least a portion of the accumulated data may be written in a lower page of the MLC non-volatile memory devices and the space in the buffer that stores data written to the lower page may be de-allocated when all higher-order pages corresponding to the lower page have been written in the MLC non-volatile memory devices. | 05-15-2014 |
20140136927 | ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE - Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time. | 05-15-2014 |
20140149826 | DATA RELIABILITY SCHEMES FOR DATA STORAGE SYSTEMS - A data storage system configured to implement a data reliability scheme is disclosed. In one embodiment, a data storage system controller detects uncorrectable errors using intra page parity when data units are read from a set of pages. When an uncorrectable error is detected, the data storage system controller attempts to recover user data using inter page parity without using all data from each page of the set of pages. Recovery of user data can thereby be performed without reading all data from each page. As a result, the amount of time needed to read data can be reduced in some cases and overall data storage system performance can be increased. | 05-29-2014 |
20140157078 | METHODS, SOLID STATE DRIVE CONTROLLERS AND DATA STORAGE DEVICES HAVING A RUNTIME VARIABLE RAID PROTECTION SCHEME - A data storage device may comprise a flash controller and an array of flash memory devices coupled to the flash controller. The array may comprise a plurality of S-Pages that may each comprise a plurality of F-Pages. In turn, each of the plurality of F-Pages may be configured to store a variable amount of data and a variable amount of error correction code. The flash controller may be configured to generate an error correction code across each F-Page of an S-Page and to store the generated error correction code within one or more F-Pages having the largest amount of data. | 06-05-2014 |
20140164457 | EXTENSIBLE ITERATIVE MULTIPLIER - An extensible iterative multiplier design is provided. Embodiments provide cascaded 8-bit multipliers for simplifying the performance of multi-byte multiplications. Booth encoding is performed in the lowest order multiplier, with the result of the Booth encoding then provided to higher order multipliers. Additionally, multiply-add operations can be performed by initializing a partial product sum register. Configurable connections between the multipliers facilitate a variety of possible multiplication options, including the possibility of varying the width of the operands. | 06-12-2014 |
20140195779 | SOFTWARE BASED APPLICATION SPECIFIC INTEGRATED CIRCUIT - A processing device is provided. A cluster includes a plurality of groups of processing elements. A multi-word device is connected to the processing elements within the groups. Each processing element in a particular group is in communication with all other processing elements within the particular group, and only one of the processing elements within other groups in the cluster. Each processing element is limited to operations in which input bits can be processed and an output obtained without reference to other bits. The multi-word device is configured to cooperate with at least two other processing elements to perform processing that requires reference to other bits to obtain a result. | 07-10-2014 |
20140250263 | TECHNIQUES FOR REDUCING MEMORY WRITE OPERATIONS USING COALESCING MEMORY BUFFERS AND DIFFERENCE INFORMATION - A system, method, and computer program product are provided for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information associated with the difference is stored in the memory. To this end, the write operations may be reduced, utilizing the difference information. | 09-04-2014 |
20140268536 | HIGH DENSITY SERVER STORAGE UNIT - A rack mountable 1U storage unit includes a plurality of memory modules arranged in two groups. The storage unit also has control circuitry. The memory modules have a dedicated exhaust channel to draw heat away from the memory modules. The exhaust channel for the memory modules is disposed over and is physically separated from the exhaust channel for the control circuitry. The storage unit can accommodate up to 42 memory modules due to a unique method of placing the individual memory modules. | 09-18-2014 |
20140280356 | APPARATUS AND METHOD FOR USING FIELDS IN N-SPACE TRANSLATION OF STORAGE REQUESTS - A translation system can translate a request having multiple fields to a physical address using the fields as indexes to a multi-dimensional graph. A field or portion of a field can represent a location along an axis. When combined together, the fields can represent a point in n-space, where n is the number of axes. In some embodiments, a nearest neighbor calculation can be sufficient along an axis. Therefore, a point in n-space defined by the fields can be translated along an axis until a nearest neighbor entry is determined. When the entry is determined, the entry can be accessed to determine a correct response to the translation request. | 09-18-2014 |
20140281167 | COMPRESSOR RESOURCES FOR HIGH DENSITY STORAGE UNITS - In various embodiments, a high-density solid-state storage unit includes a plurality of flash cards. Each flash card has a flash controller that incorporates one or more resources for facilitating compression and decompression operations. In one aspect, data reduction and data reconstruction operations can be performed in-line as data is stored to and retrieved from flash memory. In another aspect, data reduction and data reconstruction operations can be performed as a service. Any one of the plurality of flash cards can be used to provide data reduction or data reconstruction services on demand for any type of data, including system data, libraries, and firmware code. | 09-18-2014 |
20140281216 | VERTICALLY INTEGRATED STORAGE - Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. Techniques are described for vertically integrating the various software functions and hardware functions for accessing storage hardware. In some embodiments, the system is implemented using non-volatile memory. | 09-18-2014 |
20140281312 | APPARATUS AND METHOD FOR TRANSLATION FROM MULTI-DIMENSIONAL TOLINEAR ADDRESS SPACE IN STORAGE - A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. By using a map table, multiple storage services can be condensed into a single map traversal. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A node entry of root nodes or inner nodes can include a link to a next node. A node entry of a leaf node can include a physical address. Using the request fields as a key to a node, a node entry can be determined. A pointer in a root node entry or inner node entry can be followed to a next node. A physical address in a leaf node can be the translation of the storage request. | 09-18-2014 |
20140281313 | APPARATUS AND METHOD FOR CLONING AND SNAPSHOTTING IN MULTI-DIMENSIONAL TO LINEAR ADDRESS SPACE TRANSLATION - A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When snapshotting a dataset, a snapshot value can be updated in a root node entry. New data can be added under the new snaphsot value, preventing overwriting of the prior data, providing deduplication and quick snapshotting. When cloning a dataset, a new root node entry can be made for the clone. The new root entry can reference the original root entry of the original dataset. Metadata of nodes of the clone branch can identify whether the current branch contains updated data or whether the data exists off of the original root entry. | 09-18-2014 |
20140281315 | MASS STORAGE DEVICE AND METHOD OF OPERATING THE SAME TO BACK UP DATA STORED IN VOLATILE MEMORY - A mass storage memory device is disclosed. The device includes a nonvolatile memory, a volatile memory configured to store logical to physical (L2P) data associating logical addresses of data stored in the nonvolatile memory with physical locations of the nonvolatile memory at which the data is stored, and a controller. The controller writes L2P data in the nonvolatile memory so the L2P data can be preserved through a power failure. The controller also writes L2P data stored in the nonvolatile memory to the volatile memory to rebuild the L2P table. | 09-18-2014 |
20140281359 | APPARATUS AND METHOD FOR REFERENCING DENSE AND SPARSE INFORMATION IN MULTI-DIMENSIONAL TO LINEAR ADDRESS SPACE TRANSLATION - A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A hashed storage area can enable a quick lookup of densely addressed information by using a portion of the key to determine a location of a node entry. A sorted storage area can enable compact storage of sparse information by storing node entries that currently exist and allowing the entries to be searched. By offering both types of storage in a node, a node can be optimized for both dense and sparse information. A node entry can include a link to a next node or the physical address for the storage request. | 09-18-2014 |
20140281360 | APPARATUS AND METHOD FOR INSERTION AND DELETION IN MULTI-DIMENSIONAL TO LINEAR ADDRESS SPACE TRANSLATION - A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When adding node entries to a node, a node utilization can exceed a threshold value. A new node can be created such that node entries are split between the original and new node. Node metadata of the parent node, new node and original node can be revised to identify which parts of the key are used to identify a node entry. When removing node entries from a node, node utilization can cross a minimum threshold value. Node entries from the node can be merged with a sibling, or the map can be rebalanced. | 09-18-2014 |
20140281691 | MASS STORAGE DEVICE AND METHOD OF OPERATING THE SAME TO STORE PARITY DATA - A mass storage memory device is disclosed. The device includes a plurality of blades where two blades are used to store parity data corresponding to data stored in the other blades. The device also includes a controller configured to write data to the blades along stripes extending from the other blades to the two blades, where the parity data within a stripe is based on the data written to the other blades in the stripe, and wherein the parity data includes two or more types of parity data. | 09-18-2014 |
20140301143 | TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY - In operation, respective lifetime expectancy scores are calculated for each of a plurality of blocks of a memory based on a respective count percentage of free space of each of the blocks. The blocks are recycled based on at least some of the life expectancy scores. A total amount of the blocks that are re-written is minimized while equalizing lifetime expectancy score variation between the blocks. | 10-09-2014 |
20140344616 | TECHNIQUES FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES - A storage subsystem receives writes via a storage subsystem interface and reduces a number of the writes. Data associated with the reduced number of writes is stored in storage devices of a single drive. Computed redundancy information is stored in the storage devices. A data redundancy scheme is implemented via a disk controller that is enabled to operate without a loss of data in the presence of at least a single failure of any of the storage devices. | 11-20-2014 |
20150052295 | ADDRESS TRANSLATION FOR A NON-VOLATILE MEMORY STORAGE DEVICE - Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium. | 02-19-2015 |
20150077922 | HIGH CAPACITY STORAGE UNIT - A rack mountable 10U storage unit includes a plurality of memory modules arranged in multiple rows. The storage unit also has control circuitry. Each of the memory modules have multiple heating zones and a heat spreader coupled to it. The memory modules may have heat spreaders having differing thermal dissipation capacity coupled to them. The storage unit can accommodate up to 120 memory modules due to a unique method of placing the individual memory modules. | 03-19-2015 |