Patent application number | Description | Published |
20140183673 | Magnetic Read Head with MR Enhancements - A TMR stack or a GMR stack, ultimately formed into a sensor or MRAM element, include insertion layers of Fe or iron rich layers of FeX in its ferromagnetic free layer and/or the AP1 layer of its SyAP pinned layer. X is a non-magnetic, metallic element (or elements) chosen from Ta, Hf, V, Co, Mo, Zr, Nb or Ti whose total atom percent is less than 50%. The insertion layers are between 1 and 10 angstroms in thickness, with between 2 and 5 angstroms being preferred and, in the TMR stack, they are inserted adjacent to the interfaces between a tunneling barrier layer and the ferromagnetic free layer or the tunneling barrier layer and the AP1 layer of the SyAP pinned layer in the TMR stack. The insertion layers constrain interdiffusion of B and Ni from CoFeB and NiFe layers and block NiFe crystalline growth. | 07-03-2014 |
20140210022 | Magnetic Seed for Improving Blocking Temperature and Shield to Shield Spacing in a TMR Sensor - The blocking temperature of the AFM layer in a TMR sensor has been raised by inserting a magnetic seed layer between the AFM layer and the bottom shield. This gives the device improved thermal stability, including improved SNR and BER. | 07-31-2014 |
20140252518 | High Moment Wrap-Around Shields for Magnetic Read Head Improvements - A wrap around shield structure is disclosed for biasing a free layer in a sensor and includes a bottom shield, side shields, and top shield in which each shield element comprises a high moment layer with a magnetization saturation greater than that of Ni | 09-11-2014 |
20150108593 | Magnetic Seed for Improving Blocking Temperature and Shield to Shield Spacing in a TMR Sensor - The blocking temperature of the AFM layer in a TMR sensor has been raised by inserting a magnetic seed layer between the AFM layer and the bottom shield. This gives the device improved thermal stability, including improved SNR and BER. | 04-23-2015 |
20150295168 | Magnetic Read Head with MR Enhancements - A TMR stack or a GMR stack, ultimately formed into a sensor or MRAM element, include insertion layers of Fe or iron rich layers of FeX in its ferromagnetic free layer and/or the AP1 layer of its SyAP pinned layer. X is a non-magnetic, metallic element (or elements) chosen from Ta, Hf, V, Co, Mo, Zr, Nb or Ti whose total atom percent is less than 50%. The insertion layers are between 1 and 10 angstroms in thickness, with between 2 and 5 angstroms being preferred and, in the TMR stack, they are inserted adjacent to the interfaces between a tunneling barrier layer and the ferromagnetic free layer or the tunneling barrier layer and the AP1 layer of the SyAP pinned layer in the TMR stack. The insertion layers constrain interdiffusion of B and Ni from CoFeB and NiFe layers and block NiFe crystalline growth. | 10-15-2015 |
Patent application number | Description | Published |
20080309963 | PRINT IMAGE MATCHING PARAMETER EXTRACTION AND RENDERING ON DISPLAY DEVICES - Techniques are described for automatic print image matching (PIM) parameter extraction. An original image is captured and PIM parameter data is extracted automatically based on specifics of the original image. At least one automated PIM parameter is calculated automatically from the PIM parameter data. At least one automated PIM parameter is inserted in PIM header information for communication to a rendering device to modify the original image when rendered. | 12-18-2008 |
20090096899 | METHOD AND APPARATUS FOR ANISOTROPIC DEMOSAICING OF IMAGE DATA - A method and apparatus for determining missing color pixel values in image data. Pixel values are interpolated in a horizontal or a vertical direction based on gradient scores and optionally chroma and local statistical scores. Several techniques for refining the interpolation direction determination are also disclosed, including applying a low-pass filter, applying one or more digital filters, and growing an interpolation direction region to nearby pixels. A technique for interpolating corner pixel values is also disclosed. | 04-16-2009 |
20090097743 | METHOD AND APPARATUS PROVIDING HARDWARE-EFFICIENT DEMOSAICING OF IMAGE DATA - A method and apparatus for determining missing color pixel values in image data (i.e., for demosaicing image data) using a small number of lines in a buffer memory. Pixel values are interpolated in a horizontal or a vertical direction based on gradient scores. Interpolation direction selection can be refined based on a chroma scores or morphological operations. A chroma blurring technique to reduce false color artifacts is also disclosed. A disclosed embodiment can be implemented in an imager having as few as three buffer lines. | 04-16-2009 |
20090195551 | Systems and methods to achieve preferred imager color reproduction - A method and apparatus for processing image pixel signals having at least two color components in which at least some of the image pixel signals are classified into a plurality of classifications and transformed by a transform function associated with the classifications. | 08-06-2009 |
20090196498 | SYSTEM AND METHOD FOR REDUCING COLOR ARTIFACTS IN DIGITAL IMAGES - Systems and methods for reducing color artifacts in digital images. A disclosed embodiment includes averaging original color pixel values of a subject pixel in a first color domain (e.g., red, green, and blue values when operating on demosaiced pixels in the Bayer domain) with respective color pixel values of adjacent pixels, converting the average color pixel values to a second color domain, determining replacement color pixel values in the first color domain based on the color pixel values in the second color domain, and replacing the original color pixel values of the subject pixel with the replacement color pixel values. Embodiments can be repeated for some or all pixels in a digital image to reduce color artifacts across a portion of the image or the entire image, and can be performed during or at any time after demosaicing. | 08-06-2009 |
20090214129 | Apparatuses and methods for noise reduction - Methods and apparatuses provide noise reduction in a demosaiced digital image by processing the digitized signals received from a color pattern pixel array for noise reduction previous to, or as part of, a demosaicing process by using a weight matrix. | 08-27-2009 |
20120105675 | SYSTEMS, METHODS, AND APPARATUS FOR EXPOSURE CONTROL - Systems, methods and apparatus for image processing by classifying pixels are described. In some systems, an exposure control operation is performed according to the pixel classifications. In some cases, the pixels are classified according to a predetermined segmentation of a color space, based on predicted sensor responses. | 05-03-2012 |
20120176507 | SYSTEMS, METHODS, AND APPARATUS FOR IMAGE PROCESSING, FOR COLOR CLASSIFICATION, AND FOR SKIN COLOR DETECTION - Embodiments include a method of image processing including decomposing a reflectance spectrum for a test surface into a linear combination of reflectance spectra of a set of test targets. The coefficient vector calculated in this decomposition is used to predict a response of an imaging sensor to the test surface. A plurality of such predicted responses may be used for various applications involving color detection and/or classification, including human skin tone detection. | 07-12-2012 |
20140359559 | AUTOMATED GRAPH-BASED PROGRAMMING - A method includes capturing an image of a scene that includes a diagram. The method further includes applying functional block recognition rules to image data of the image to recognize functional blocks of the diagram. The functional blocks include at least a first functional block associated with a first computer operation. The method further includes determining whether the functional blocks comply with functional block syntax rules. A functional graph is computer-generated based on the functional blocks complying with the functional block syntax rules. The functional graph corresponds to the diagram, and the functional graph includes the functional blocks. | 12-04-2014 |
20140359563 | EFFICIENT EXECUTION OF GRAPH-BASED PROGRAMS - A method includes accessing, at a computing device, data descriptive of a graph representing a program. The graph includes multiple nodes representing execution steps of the program and includes multiple edges representing data transfer steps. The method also includes determining at least two heterogeneous hardware resources of the computing device that are available to execute code represented by one or more of the nodes, and determining one or more paths from a source node to a sink node based on a topology of the graph. The method further includes scheduling execution of code at the at least two heterogeneous hardware resources. The code is represented by at least one of the multiple nodes, and the execution of the code is scheduled based on the one or more paths. | 12-04-2014 |
20150058579 | SYSTEMS AND METHODS FOR MEMORY UTILIZATION FOR OBJECT DETECTION - A method for memory utilization by an electronic device is described. The method includes transferring a first portion of a first decision tree and a second portion of a second decision tree from a first memory to a cache memory. The first portion and second portion of each decision tree are stored contiguously in the first memory. The first decision tree and second decision tree are each associated with a different feature of an object detection algorithm. The method also includes reducing cache misses by traversing the first portion of the first decision tree and the second portion of the second decision tree in the cache memory based on an order of execution of the object detection algorithm. | 02-26-2015 |
20150254824 | SYSTEM AND METHOD OF PERFORMING MULTI-LEVEL INTEGRATION - A particular method includes generating a first result of a first integration operation performed on a first subset of elements of the plurality of elements. The first integration operation is associated with a first level of integration. The method includes generating a second result of a second integration operation performed on the first subset of elements. The second integration operation is associated with a second level of integration. The method further includes performing a third integration operation on a second subset of elements of the plurality of elements. The third integration operation is associated with the second level of integration. The third integration operation is performed based on the first result and the second result. | 09-10-2015 |
20150379740 | EXPOSURE METERING BASED ON BACKGROUND PIXELS - The disclosed technology relates to image-capturing methods. In one aspect, a method includes receiving an image frame comprising a plurality of pixels and subtracting foreground pixels from the image frame to obtain background pixels. The method additionally includes determining an exposure condition for a next image frame based on at least a subset of the background pixels. The method further includes adjusting the foreground pixels such that a difference between a background luma value and a foreground luma value of the next image frame is within a predetermined range. Aspects are also directed to apparatuses configured for the methods. | 12-31-2015 |
Patent application number | Description | Published |
20090009375 | LOW POWER, LOW NOISE DIGITAL-TO-ANALOG CONVERTER REFERENCE CIRCUIT - The present patent application comprises a digital to analog converter reference circuit, comprising a capacitor connected to a current source, a positive terminal of the capacitor connected to a first switch, the first switch electrically connecting the positive terminal of the capacitor to a positive input terminal of a DAC circuit, a negative terminal of the capacitor connected to a second switch, the second switch electrically connecting the negative terminal of the capacitor to a negative input terminal of the DAC circuit. | 01-08-2009 |
20090021409 | DYNAMIC SLEW RATE CONTROL BASED ON A FEEDBACK SIGNAL - Techniques for enhancing the slew rate of an active circuit within a feedback circuit (such as a ΔΣ ADC) are described. In one design, a ΔΣ ADC includes an integrator, a slew rate enhancement circuit, and a control circuit. The integrator receives an input signal and provides an output signal. The slew rate enhancement circuit enhances the slew rate of the integrator based on a feedback signal in the ΔΣ ADC. The slew rate enhancement circuit may provide (i) a boost current for only certain values (e.g., the largest and smallest values) of the feedback signal or (ii) different amounts of boost current for different values of the feedback signal. In one design, the slew rate enhancement circuit includes at least one boost circuit coupled to the integrator. Each boost circuit provides a boost current to enhance the slew rate of the integrator when that boost circuit is enabled. | 01-22-2009 |
20090091393 | DUAL-PATH CURRENT AMPLIFIER - A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor. | 04-09-2009 |
20100026542 | ADAPTIVE BIAS CURRENT GENERATION FOR SWITCHED-CAPACITOR CIRCUITS - Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ΣΔ ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations. | 02-04-2010 |
20100253405 | TECHNIQUES FOR NON-OVERLAPPING CLOCK GENERATION - Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (t | 10-07-2010 |
20100283522 | ALL-DIGITAL SELECTABLE DUTY CYCLE GENERATION - All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator. | 11-11-2010 |
20110063005 | DELAY-LOCKED LOOP HAVING A DELAY INDEPENDENT OF INPUT SIGNAL DUTY CYCLE VARIATION - A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal. | 03-17-2011 |
20110260753 | Level Shifter with Balanced Duty Cycle - A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element. | 10-27-2011 |
20120015617 | Squelch Detection Circuit and Method - A squelch detection circuit and method involves a first comparator coupled to a complimentary input signal pair and having a first polarity output. A second comparator coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold. | 01-19-2012 |
20120161837 | NON-OVERLAPPING CLOCK GENERATION - Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (t | 06-28-2012 |
20120194253 | High Voltage Tolerant Differential Receiver - A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry. | 08-02-2012 |
20120194254 | High Voltage Tolerant Receiver - A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit. | 08-02-2012 |
20120212265 | DELAY CELL FOR CLOCK SIGNALS - An integrated circuit for delaying a clock signal using a delay cell is described. The integrated circuit includes a current starved inverter. The current starved inverter includes a switched capacitor current source with a first dummy inverter, a first amplifier coupled to the first dummy inverter and a first capacitor coupled to the first amplifier via a first switch. The current starved inverter also includes a first transistor coupled to the current source. The integrated circuit also includes a second capacitor. A delay applied to the clock signal is dependent on a ratio between the first capacitor and the second capacitor. The first capacitor and the second capacitor may be located in proximity such that process, voltage and temperature variations affect the first capacitor and the second capacitor similarly and the delay applied to the clock signal is independent of process, voltage and temperature variations. | 08-23-2012 |
20120235730 | CHARGE PUMP SURGE CURRENT REDUCTION - Techniques for reducing surge current in charge pumps. In an exemplary embodiment, one or more switches coupling a terminal of a flying capacitor to a voltage supply are configured to have variable on-resistance. When the charge pump is configured to switch a gain mode from a lower gain to a higher gain, the one or more variable resistance switches are configured to have a decreasing resistance profile over time. In this manner, surge current drawn from the voltage supply at the outset of the gain switch may be limited, while the on-resistance during steady-state charging and discharging may be kept low. Similar techniques are provided to decrease the surge current from a bypass switch coupling the supply voltage to a positive output voltage of the charge pump. | 09-20-2012 |
20120236444 | CHARGE PUMP ELECTROSTATIC DISCHARGE PROTECTION - Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2. | 09-20-2012 |
20130223649 | LOAD CURRENT SENSING - Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors. | 08-29-2013 |
20140029611 | SYSTEMS AND METHODS FOR SHARING A SERIAL COMMUNICATION PORT BETWEEN A PLURALITY OF COMMUNICATION CHANNELS - An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active. | 01-30-2014 |
20140103897 | GLITCH SUPPRESSION IN DC-TO-DC POWER CONVERSION - Exemplary embodiments are directed to devices and method for operating a charge pump. A method may include activating a first switch coupled between a capacitor and a ground voltage over a first period of a charging phase. The first period may coincide with a non-overlapping time between the charging phase and an output phase. The method may also include activating a second switch coupled between the capacitor and an input voltage over a second period of the charging phase, wherein the first period begins prior to the second period. Further, the method may include deactivating the second switch over a third period of the charging phase and deactivating the first switch over a fourth period of the charging phase, wherein the third period begins prior to the fourth period. | 04-17-2014 |
20140177850 | SWITCH TECHNIQUES FOR LOAD SENSING - Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor. | 06-26-2014 |
Patent application number | Description | Published |
20110183621 | METHOD AND APPARATUS FOR SPECTRAL SENSING - An apparatus for wireless communication includes a processing system. The processing system is configured to estimate a power spectral density of a first signal. In addition, the processing system is configured to determine a normalized correlation detector between the estimated power spectral density and a known power spectral density of a second signal. Furthermore, the processing system is configured to determine whether the first signal contains the second signal based on the normalized correlation detector. | 07-28-2011 |
20130072214 | SYSTEM, METHOD AND APPARATUS FOR ALLOCATING WIRELESS CHANNELS IN A MULTI-CHANNEL ACCESS POINT - Methods and apparatus provide for channel selection within a wireless network. A multi-channel wireless access point may select a channel for a wireless device requesting data or voice service based on the transmit times of each channel supported by the multi-channel wireless access point. The transmit times may be based on the physical rates of the devices assigned to each channel. The channel may also be selected based on the quality of service requested by the wireless device, the medium occupancy of each channel, or the number of wireless devices assigned to each channel. Alternatively the wireless device may select the channel for assignment based on channel statistics information provided by the multi-channel wireless access point. This information may be provided through one or more beacon signals, or supplied in response to a request for the information from a wireless device. | 03-21-2013 |
20130128808 | APPARATUS AND METHODS FOR MEDIA ACCESS CONTROL HEADER COMPRESSION - Systems, methods, and devices for communicating packets having a plurality of types are described herein. In some aspects, the packets include a compressed MAC header. In some aspects the packets include an acknowledgment (ACK) frame. The fields included in a particular packet type may be based on the type of information to be communicated to the receiving device. | 05-23-2013 |
20130128809 | APPARATUS AND METHODS FOR MEDIA ACCESS CONTROL HEADER COMPRESSION - Systems, methods, and devices for communicating packets having a plurality of types are described herein. In some aspects, the packets include a compressed MAC header. In some aspects the packets include an acknowledgment (ACK) frame. The fields included in a particular packet type may be based on the type of information to be communicated to the receiving device. | 05-23-2013 |
20130141215 | SYSTEMS AND METHODS FOR LOW OVERHEAD PAGING - Systems and methods for low overhead paging in a wireless communications network are described herein. In some aspects, an apparatus for wireless communication includes a receiver and a processor. The receiver receives a request from a first device. The request indicates a first period of a plurality of periods corresponding to a periodicity for transmitting paging messages. The processor assigns the first device to a group scheduled to receive paging messages at most every first period based on the request and determines a start time for transmitting paging messages to the first device based on schedules for transmitting paging messages to a plurality of other devices. In other aspects, an apparatus for wireless communication includes a processor and memory. The processor derives an information sub-unit from an information unit associated with a paging message, compresses the information sub-unit, and generates a second information unit associated with the method of compression. | 06-06-2013 |
20130142094 | SYSTEMS AND METHODS FOR FRAME FILTERING AND FOR ENABLING FRAME FILTERING - The disclosure provides systems, methods, and apparatus for early receive chain shutoff using a typified CRC and/or content change indicator signals. In one aspect, a method for low power frame filtering is provided. The method comprises generating a typified checksum based on a transaction identifier and at least a portion of a packet. The method further comprises transmitting, to at least one receiver, the packet comprising the typified checksum. | 06-06-2013 |
20130143606 | SYSTEMS AND METHODS FOR LOW OVERHEAD PAGING - Systems and methods for low overhead paging in a wireless communications network are described herein. In some aspects, an apparatus for wireless communication includes a receiver and a processor. The receiver receives a request from a first device. The request indicates a first period of a plurality of periods corresponding to a periodicity for transmitting paging messages. The processor assigns the first device to a group scheduled to receive paging messages at most every first period based on the request and determines a start time for transmitting paging messages to the first device based on schedules for transmitting paging messages to a plurality of other devices. In other aspects, an apparatus for wireless communication includes a processor and memory. The processor derives an information sub-unit from an information unit associated with a paging message, compresses the information sub-unit, and generates a second information unit associated with the method of compression. | 06-06-2013 |
20130176864 | RATE AND POWER CONTROL SYSTEMS AND METHODS - A method includes transmitting a packet from a first wireless device to a second wireless device, where data within the packet is encoded and a signal representing the packet is modulated in accordance with a modulation and coding scheme (MCS). The method also includes, responsive to receiving an acknowledgement packet that includes a MCS change indicator from the second wireless device via a wireless local area network (WLAN) in response to transmitting the packet, maintaining the MCS when the MCS change indicator has a first value and incrementing the MCS when the MCS has a second value. | 07-11-2013 |
20130176902 | SYSTEM AND METHOD OF COMMUNICATION USING DISTRIBUTED CHANNEL ACCESS PARAMETERS - A device includes a processor and a memory accessible by the processor. The memory includes access category data specifying one or more access categories. The one or more access categories include a sensor access category specifying distributed channel access parameters to be used by one or more station devices to wirelessly communicate sensor data via a network. The memory further includes instructions executable by the processor to send at least a portion of the access category data to a station device to enable the station device to communicate sensor data. | 07-11-2013 |
20130188542 | SYSTEMS AND METHODS OF RELAY SELECTION AND SETUP - A particular method includes receiving, at an access point, one or more request messages from one or more relay nodes, each of the one or more request messages is a probe request message or an association request message related to a station. The method includes selecting a communication path between the access point and the station based on the one or more request messages and sending a response message indicating the selected communication path. | 07-25-2013 |
20130208667 | DEVICES FOR REDUCED OVERHEAD PAGING - A method for reduced overhead paging by an access point is described. The method includes assigning at least one paging identifier to at least one station. The method also includes partitioning a paging identifier space into paging identifier sets. The method further includes generating a paging message based on at least one of the paging identifier sets and the at least one paging identifier. The method additionally includes sending the paging message. | 08-15-2013 |
20130215836 | SYSTEMS AND METHODS FOR COMPRESSING HEADERS - A method includes assigning a flow identifier to a flow that includes a plurality of packets. The method also includes generating a head packet of the plurality of packets. The head packet includes one or more header information fields that are associated with the flow identifier. The method further includes generating at least one data packet of the plurality of packets. The at least one data packet includes packet specific information and the flow identifier instead of the one or more header information fields. The method further includes transmitting the head packet. The method further includes, in response to detecting a successful receipt of the head packet, transmitting the at least one data packet. | 08-22-2013 |
20130223210 | APPARATUS AND METHODS FOR BLOCK ACKNOWLEDGMENT COMPRESSION - Systems, methods, and devices for compressing block acknowledgment (ACK) frames/packets are described herein. In some aspects, a method of communicating in a wireless network includes generating a compressed block acknowledgment frame comprising one or more local addresses. The method further includes transmitting the compressed block acknowledgment frame. | 08-29-2013 |
20130223211 | APPARATUS AND METHODS FOR BLOCK ACKNOWLEDGMENT COMPRESSION - Systems, methods, and devices for compressing block acknowledgment (ACK) frames/packets are described herein. In some aspects, a method of communicating in a wireless network includes generating a compressed block acknowledgment frame including one or more of the following fields in a physical layer header: duration, receiver address, transmitter address, block acknowledgment control, block acknowledgment policy, compressed bitmap, compression control, starting sequence number. The method further includes transmitting the compressed block acknowledgment frame. | 08-29-2013 |
20130223212 | APPARATUS AND METHODS FOR BLOCK ACKNOWLEDGMENT COMPRESSION - Systems, methods, and devices for compressing block acknowledgment (ACK) frames/packets are described herein. In some aspects, a method of communicating in a wireless network includes generating a compressed block acknowledgment frame comprising a physical layer header, the physical layer header including at least one of the following: a block acknowledgment identifier, a starting sequence number of the compressed block acknowledgement frame, and a bitmap. The method further includes transmitting the compressed block acknowledgment frame. | 08-29-2013 |
20130223213 | APPARATUS AND METHODS FOR BLOCK ACKNOWLEDGMENT COMPRESSION - Systems, methods, and devices for compressing block acknowledgment (ACK) frames/packets are described herein. In some aspects, a method of communicating in a wireless network includes a compressed block acknowledgment frame including a bitmap, the bitmap indicating receipt of a plurality of fragments of a single data unit. The method further includes transmitting the compressed block acknowledgment frame. | 08-29-2013 |
20130223338 | APPARATUS AND METHODS FOR BLOCK ACKNOWLEDGMENT COMPRESSION - Systems, methods, and devices for compressing block acknowledgment (ACK) frames/packets are described herein. In some aspects, a method of compressing a block acknowledgment frame includes generating an offset value and a portion of a bitmap, the offset value indicating a location where the portion of the bitmap is located in the bitmap. The method further includes transmitting the offset value and the portion of the bitmap in a compressed block acknowledgment frame. | 08-29-2013 |
20130223345 | APPARATUS AND METHODS FOR BLOCK ACKNOWLEDGMENT COMPRESSION - Systems, methods, and devices for compressing block acknowledgment (ACK) frames/packets are described herein. In some aspects, a method of communicating in a wireless network includes generating a block acknowledgment frame comprising a plurality of fields in the following order: a block acknowledgment identifier field including an identifier of the block acknowledgment frame; a starting sequence control field including at least one of a sequence number and a function of a sequence number of a data unit for which the block acknowledgement frame is sent; and a block acknowledgement bitmap field indicating a received status of a number of data units. The method further includes wirelessly transmitting the block acknowledgment frame. | 08-29-2013 |
20130223422 | SYSTEMS AND METHODS FOR OPTIMIZING WIRELESS TRANSMISSION DATA RATES - One aspect of the disclosure provides a method for wireless communication. The method includes sending a modulation and coding scheme request to an access point. The modulation and coding scheme request is sent using a first physical layer preamble frame. The modulation and coding scheme request includes an identifier associated with the access point. The method further includes receiving at a station a modulation and coding scheme feedback response from the access point in response to sending the modulation and coding scheme request. The modulation and coding scheme feedback response is received as a second physical layer preamble frame. In addition, the method includes determining a modulation and coding scheme based on the modulation and coding scheme feedback response. Moreover, the method includes transmitting data to the access point using the identified modulation and coding scheme. | 08-29-2013 |
20130227371 | BLOCK ACKNOWLEDGEMENT MECHANISM INCLUDING SEQUENCE NUMBER ACKNOWLEDGEMENT AND RETRY BIT - A method includes sending a sequence number acknowledgement (SN-ACK) from a first device to a second device. The SN-ACK identifies a last consecutively correctly received data unit and includes a retry bit indicating whether at least one data unit of the plurality of data units was received by the first device subsequent to the last consecutively correctly received data unit. The method also includes, when the retry bit has a first value, sending a block acknowledgement (BA) after sending the SN-ACK. The BA includes a bitmap, where each particular bit of the bitmap indicates whether a corresponding data unit was correctly received. When the retry bit has a second value and one or more of the plurality of data units were incorrectly received by the first device, the first device receives a retransmission of one or more data units without sending the BA to the second device. | 08-29-2013 |
20130230059 | FRAGMENTATION FOR LONG PACKETS IN A LOW-SPEED WIRELESS NETWORK - A method includes creating a plurality of data fragments from a single data unit. The method also includes transmitting the plurality of data fragments to a receiver and receiving an acknowledgement from the receiver after transmitting a last data fragment of the plurality of data fragments. The method further includes selectively interpreting the acknowledgement as a multi-fragment acknowledgement (MFA) in response to a value of a fragment sequence number (FGSN) of the last data fragment. The MFA indicates receipt or non-receipt by the receiver of each of the plurality of data fragments of the single data unit. | 09-05-2013 |
20130235737 | DEFERRAL MECHANISM FOR IMPROVED MEDIUM REUSE IN WIRELESS NETWORKS WITH TRANSMIT POWER IMBALANCES - The deferral mechanism described herein may improve medium reuse in a wireless network with transmit power imbalances. For example, in one embodiment, an apparatus employing the deferral mechanism described herein may comprise a receiver to sense a data unit transmitted on a medium associated with the wireless network, wherein the data unit may comprise information indicating a transmit power associated therewith. Furthermore, the apparatus may comprise one or more processors to initiate a transmission on the medium associated with the wireless network if the apparatus is not an intended receiver of the sensed data unit, the transmit power associated with the data unit exceeds a transmit power associated with the apparatus, and a received power associated with the data unit does not equal or exceed a clear channel assessment threshold plus a difference between the transmit power associated with the data unit and the transmit power associated with the apparatus. | 09-12-2013 |
20130235781 | SYSTEMS AND METHODS FOR ACKNOWLEDGING COMMUNICATIONS FROM A PLURALITY OF DEVICES - Systems, methods, and devices for acknowledging communications from a plurality of wireless devices in a wireless network are described herein. In some embodiments, an access point for the wireless network transmits a group acknowledgment (ACK) to indicate whether communications (packets) from the plurality of wireless devices have been received or correctly decoded within some time interval. Each wireless device may have a different time interval associated with it. For some embodiments, the time interval for a wireless device is relative to when a previous group ACK was sent. A group ACK may include a bitmap. In some embodiments, the bitmap indicating whether a communication has been received or correctly decoded may be transmitted as part of a beacon. | 09-12-2013 |
20130272211 | SCHEDULING ALGORITHMS FOR IEEE 802.11 MULTI-USER (MU) MULTIPLE-INPUT MULTIPLE-OUTPUT (MIMO) COMMUNICATION SYSTEMS - A method is provided for wirelessly transmitting from a transmitter to one or more receivers within a multi-user (MU) multiple-input and multiple-output (MIMO) communication system. A number of concurrent (spatial) streams are dynamically allocated in a MU-MIMO transmission to each of a plurality of served receivers to maximize total data transmitted on each transmission. Streams are allocated according to a corresponding transmission queue length for each receiver and the number of receive antennas used by each of the served receivers. A transmission timer is started upon sending the transmission. A random backoff counter is also started upon one of either: (a) expiration of the transmission timer or (b) receipt of data at a transmission queue. A new transmission is sent upon expiration of the random backoff counter if the transmission timer has expired. Otherwise, the random backoff counter is restarted one or more times until the transmission timer has expired. | 10-17-2013 |
20130279427 | SYSTEM AND METHOD OF COMMUNICATION USING DISTRIBUTED CHANNEL ACCESS PARAMETERS - A method includes in response to receiving a modified enhanced distributed channel access (EDCA) parameter set IE at a station, determining a value of an EDCA parameter based on a delta value in the modified EDCA parameter set IE and based on a base value of the EDCA parameter. | 10-24-2013 |
20150029839 | APPARATUS AND METHODS FOR BLOCK ACKNOWLEDGMENT COMPRESSION - Systems, methods, and devices for compressing block acknowledgment (ACK) frames/packets are described herein. In some aspects, a method of communicating in a wireless network includes a compressed block acknowledgment frame including a bitmap, the bitmap indicating receipt of a plurality of fragments of a single data unit. The method further includes transmitting the compressed block acknowledgment frame. | 01-29-2015 |
Patent application number | Description | Published |
20130170345 | SYSTEMS AND METHODS FOR GENERATING AND DECODING SHORT CONTROL FRAMES IN WIRELESS COMMUNICATIONS - Systems, methods, and devices for communicating short control frames are described herein. In some aspects, a method of wireless communication includes generating a control frame comprising a physical layer preamble having a signal field, the signal field including an indicator indicating the control frame is a control frame type of frame. The method further includes transmitting the control frame. | 07-04-2013 |
20130201974 | SYSTEMS AND METHODS FOR REDUCING COLLISIONS AFTER TRAFFIC INDICATION MAP PAGING - Systems, methods, and devices for reducing collisions in a wireless communications network are described herein. In some aspects, a processor is configured to decrementing a value of a counter if a channel of a wireless communications network is idle for at least an extended slot time. The processor may be further configured to generate a polling request and allow the transmission of the polling request to an access point over the wireless communications network when the value of the counter reaches a threshold value. | 08-08-2013 |
20130208637 | SYSTEMS AND METHODS FOR ACCESS POINT TRIGGERED TRANSMISSIONS AFTER TRAFFIC INDICATION MAP PAGING - Systems, methods, and devices for reducing collisions in a wireless communications network are described herein. In one aspect an apparatus for wireless communication is provided. The apparatus includes a transmitter configured to transmit a first message over a communication medium to a plurality of nodes configured to be selectively at least partially powered down during time periods in which the first message is not expected to be transmitted. The first message indicates a subset of the plurality of nodes for which data is available for transmission. The apparatus further includes a controller configured to initiate a process for transmitting the data available to the subset of the plurality of nodes after the first message is transmitted. | 08-15-2013 |
20130229963 | SYSTEMS AND METHODS FOR REDUCING COLLISIONS AFTER TRAFFIC INDICATION MAP PAGING - Systems, methods, and devices for reducing collisions in a wireless communications network are described herein. In some aspects, a receiver receives a paging message. The paging message includes an ordering and a multiplier. A processor determines a first wake-up time based on the ordering and the multiplier. The wireless device wakes up at the determined wake-up time. The wireless device receives data via the receiver. | 09-05-2013 |
20130229969 | APPARATUS AND METHODS FOR ACCESS IDENTIFIER BASED MULTICAST COMMUNICATION - Systems, methods, and devices for multicast communications including access identifiers are described herein. In some aspects, a fixed mapping from a multicast device identifier (e.g., multicast MAC address, multicast IP address) to a multicast access identifier is provided. In some aspects, a device may transmit a request to join a multicast group identified by a multicast access identifier. In some aspects, a device may receive an invitation to join a multicast group identified by a multicast access identifier. | 09-05-2013 |
20130235760 | SYSTEMS AND METHODS FOR ESTABLISHING A CONNECTION SETUP THROUGH RELAYS - Systems, methods, and devices for discovering a wireless communications network are described herein. In some aspects, a transmitter of a station is configured to transmit a probe request. The probe request is addressed to one of a wildcard service set identifier and a service set identifier of a service set in which a relay operates. A receiver of the station is configured to receive a probe request response from the relay. The probe response comprises an identification of an access point the relay is associated with and capabilities of the relay. | 09-12-2013 |
20130235788 | SYSTEMS AND METHODS FOR ESTABLISHING A CONNECTION SETUP THROUGH RELAYS - Systems, methods, and devices for communicating data in a wireless communications network are described herein. In some aspects, an access point is configured to receive a request for relay connection and to transmit a message to at least one relay based on the received request for relay connection. The message comprises an instruction to transmit a setup response frame. A station is configured to transmit the request for relay connection to the access point and to select one of the at least one relay based on at least one setup response frame received from at least one of the at least one relay. The selected one of the at least one relay is configured to relay data packets between the station and the access point. | 09-12-2013 |
20130235789 | SYSTEMS AND METHODS FOR ESTABLISHING A CONNECTION SETUP THROUGH RELAYS - Systems, methods, and devices for registering a relay in a wireless communications network are described herein. In some aspects, a device is configured to operate as a relay and to transmit an association message. The association message comprises capabilities of the device and an indication of whether the device relays uplink traffic, downlink traffic, or both. An access point is configured to receive the association message to associate the device with the access point based on the association message and to transmit a beacon message to a station. The beacon message comprises an indication of whether the access point is associated with a relay. | 09-12-2013 |
20130235790 | SYSTEMS AND METHODS FOR ESTABLISHING A CONNECTION SETUP THROUGH RELAYS - Systems, methods, and devices for communicating data in a wireless communications network are described herein. In some aspects, a receiver of a relay is configured to receive a relay initiator frame and a data frame. A transmitter of the relay is configured to transmit an amplified version of the data frame at a same or substantially same time as a time that the data frame is received if the relay initiator frame is received prior to the data frame. | 09-12-2013 |
20130235791 | SYSTEMS AND METHODS FOR ESTABLISHING A CONNECTION SETUP THROUGH RELAYS - Systems, methods, and devices for setting up a relay in a wireless communications network are described herein. In some aspects, a transmitter of a station is configured to transmit a relay request to an access point. The access point is configured to transmit a discovery request frame based on the relay request to at least one relay. Each of the at least one relay is configured to transmit a discovery message based on the discovery request frame to the station. A processor of the station is configured to select one relay of the at least one relay based on each received discovery message. The transmitter is further configured to transmit a message comprising an identification of the selected one relay of the at least one relay to the access point. | 09-12-2013 |
20130235792 | SYSTEMS AND METHODS FOR ESTABLISHING A CONNECTION SETUP THROUGH RELAYS - Systems, methods, and devices for securely communicating data are described herein. In some aspects, a station is configured to communicate with an access point. A relay includes an uncontrolled port and a controlled port. The relay is configured to forward association, authentication, and secure relay setup frames between the station and the access point through the uncontrolled port. The relay is configured to forward data packets between the station and the access point through the uncontrolled port once the station establishes a relay relationship with the relay. | 09-12-2013 |
20130271286 | Methods and Systems for Monitoring Environmental Conditions Using Wireless Sensor Devices and Actuator Networks - The present invention comprises methods and systems of a network of sensor devices to monitor environmental conditions. Each sensor device is capable of acquiring environmental data and transmitting the data to a central controller of a networking system by wireless communication. By processing the environmental data obtained from the geographically deployed sensor devices, the central controller is capable of detecting a trend of the hazardous condition. The central controller generates early warning signals based on the hazardous levels of the physical or environmental conditions, as well as the trend of such conditions. When receiving a high level of hazardous conditions from one of the networked sensor devices, the central controller can compare the results with neighboring sensor devices to determine whether the signal received is due to a hazard leakage or a sensor device malfunction, so to reduce false alarms and provide feedbacks to communication devices networked in the system. | 10-17-2013 |
20130279426 | SYSTEM AND METHOD OF COMMUNICATION USING DISTRIBUTED CHANNEL ACCESS PARAMETERS - A method includes, in response to receiving a delta value of an enhanced distributed channel access (EDCA) parameter at a station, determining a value of the EDCA parameter based on the delta value and based on a base value of the EDCA parameter. The method also includes, in response to receiving an EDCA parameter set information element (IE), determining the value of the EDCA parameter based on the EDCA parameter set IE. The method further includes, in response to no delta value or EDCA parameter set IE being received at the station during a time period, setting the value of the EDCA parameter to a default value of the EDCA parameter. | 10-24-2013 |
20130315139 | METHODS, DEVICES, AND SYSTEMS FOR EFFICIENT RETRANSMISSION COMMUNICATIONS - Methods, devices, and systems for retransmitting Media Access Control (MAC) protocol data units (MPDUs) in a multi-user multiple-input and multiple-output (MU-MIMO) communication system are disclosed. Concurrent data streams within a first transmission window are transmitted. Each concurrent data stream is associated with a different recipient and includes an equal number of MPDUs. An indication of a retransmission subset of the MPDUs to be retransmitted for each concurrent data stream may be obtained if errors are present. The retransmission subset for each concurrent data stream is retransmitted within a second transmission window. A length of the second transmission window is as long as the longest of the retransmission subsets of the concurrent data streams. One or more new MPDUs may be added to the concurrent data streams in the second transmission window so that each concurrent data stream in the second transmission window carries a same number of MPDUs. | 11-28-2013 |
20140056223 | FRAGMENTATION FOR LONG PACKETS IN A LOW-SPEED WIRELESS NETWORK - A method includes determining, at a transmitter, whether the transmitter supports multi-fragment acknowledgment (MFA) based on a parameter of the transmitter. The method also includes transmitting a first frame to a receiver. A fragment block acknowledgment (BA) support sub-field of a sub-1 gigahertz (S1G) capabilities information field of a S1G capabilities element of the first frame has a first value in response to determining that the transmitter supports MFA. The fragment BA support sub-field has a second value in response to determining that the transmitter does not support MFA. | 02-27-2014 |
20140294019 | FRAGMENTATION FOR LONG PACKETS IN A LOW-SPEED WIRELESS NETWORK - A method includes receiving a data fragment of a block of data fragments of a single data unit from a wireless device at a receiver. The method includes, in response to determining that the data fragment is a last data fragment of the block of data fragments, transmitting an acknowledgement to the wireless device. The acknowledgement indicates whether each data fragment of the block of data fragments was received from the wireless device. The method includes, in response to determining that the data fragment is a last data fragment of the single data unit, transmitting the acknowledgment to the wireless device. The method further includes, in response to determining that the data fragment is not the last data fragment of the block of data fragments or the last data fragment of the single data unit, refraining from transmitting the acknowledgement to the wireless device. | 10-02-2014 |