Patent application number | Description | Published |
20090120384 | LOW BED PRESSURE DROP CIRCULATING FLUIDIZED BED BOILER AND COMBUSTION PROCESS - A method, system and apparatus for a low bed pressure drop circulating fluidized bed (CFB) boiler associated with fast bed CFB combustion are disclosed. The CFB boiler may be operated according to the following set of conditions. In an upper area of a combustor of the boiler, a flow pattern of the two-phase gas-solid flow may be placed in a fast bed fluidization state. The combustor temperature may be within a range of 850° C.-930° C. The fluidizing air velocity may be within 4 m/s and 6.2 m/s. An average size of a bed material in the combustor may be smaller than 300 μm. The gas-solid flow above of the secondary air inlet in the combustor may be kept in the fast bed fluidization state while maintaining a solid concentration of between 1 kg/m3 to 5 kg/m3. An inventory of bed material per unit area and/or the pressure drop in the combustor may be less than 8 kPa. | 05-14-2009 |
20130032628 | ANORECTAL SURGICAL INSTRUMENT AND ANAL DILATOR - An anal dilator ( | 02-07-2013 |
20130191081 | CREATING A WELL PATH - A method or methods, and systems and computer program products for performing or executing such method(s), comprising developing a well plan based on a plurality of points in three-dimensional space, refining the well plan to remove noise, smoothing the refined well plan, adjusting resolution of the smoothed well plan, converting the resolution-adjusted well plan into a plurality geometric shapes, mapping the plurality of geometric shapes to ones of a plurality of drillable shapes via image processing and pattern recognition, and optimizing the mapped well plan by synthesizing into at least one drillable profile. | 07-25-2013 |
20130331957 | Information Control Method and Electronic Device - The invention discloses an information control method and an electronic device. The information control method is applied to a first electronic device, and the first electronic device is connected with a second electronic device. The method includes: detecting feature information of the first electronic device according to a connection relation between the first electronic device and the second electronic device; and controlling the first electronic device according to the feature information. | 12-12-2013 |
20140005996 | INTERACTIVE AND THREE-DIMENSIONAL WELL PATH DESIGN | 01-02-2014 |
20140351215 | Application Management Method And Device - Disclosed are an application management method and device, applied to a first device connected to a second device. The method includes mapping at least one application in the second device, to obtain at least one corresponding application identifier; detecting a first operation; when the first operation satisfies a first preset condition, determining an application identifier of a first application according to the at least one application identifier; detecting a second operation; when the second operation satisfies a second preset condition, obtaining a corresponding application management command according to the second operation; and sending the application management command to the second device, so that the second device manages the first application according to the application management command. | 11-27-2014 |
20150077342 | INPUT APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING APPARATUS - An input apparatus, an information processing method, and an information processing apparatus are provided. The input apparatus includes a protection surface layer, and a sensing array through which an operation of a user on the protection surface layer can be determined. The information processing method can parse trigger information sent by the input apparatus for its corresponding parameter information and further switch the touchable keyboard to a first input mode or a second input mode according to the obtained parameter information. The information processing method and apparatus and the electronic device activate a keyboard to judge the demand of the user automatically in response to the trigger information entered by the user and further control switching of the input mode of the keyboard in response to the demand of the user. | 03-19-2015 |
20150077343 | INPUT DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - An input device is provided in the present application. The input device includes a first panel and a second panel, the first panel is provided with multiple grooves; the second panel is located under the first panel or fused to a bottom of the first panel, and includes a sensing unit configured to sense a key. In the input device, each of the grooves is arranged to correspond to one key area, and a key command may be input by performing a touch key operation on a corresponding sensing unit under the groove. Compared with the conventional input device, in the input device of the present application, the input of the key command may be realized without key caps and scissor-shaped structures for supporting the key caps, thereby shortening the key travel and reducing the thickness of the input device. | 03-19-2015 |
20150083777 | HANDLE FOR ELECTRIC SURGICAL STAPLER - A handle for an electric surgical stapler. The electric surgical stapler includes an end effector. The handle includes a casing, a linear motor, a power transmission mechanism, and a quick change interface. The linear motor is disposed in the casing and configured to supply linear motion. The power transmission mechanism transmits the linear motion from the linear motor to the end effector. The quick change interface is connected to the end effector. | 03-26-2015 |
20150083778 | SURGICAL STAPLER COMPRISING SAFETY APPARATUS - A surgical stapler including a safety apparatus, including: a stapler part, a fixed handle, a safety apparatus, a transmission assembly, a propulsion assembly, and a trigger handle. The safety apparatus includes a safety piece and a fixing block. The propulsion assembly includes an ejector sleeve. The safety apparatus is fixed on the propulsion assembly and contacts with a surface of the transmission assembly. The safety piece is disposed inside the fixing block. At least one spring is disposed inside the fixing block to ensure elasticity of the safety piece. | 03-26-2015 |
20150083779 | SURGICAL STAPLER - A surgical stapler, including: an anvil assembly, a reload assembly, a movable handle, a fixed handle, a transmission assembly, a propulsion assembly, a safety apparatus, and an anti-triggering device. The anti-triggering device includes two rows of holes and clamp strips. The transmission assembly is disposed inside the fixed handle. The clamp strips are arranged in longitudinal symmetry on one side of the anti-triggering device. A row of counterbores and a clamp plate having a structure matching with the clamp strip of the anti-triggering device are arranged at an inner side of the casing of the fixed handle. The safety apparatus is fixed at one side of the propulsion assembly. The anti-triggering device is clamped inside the casing of the fixed handle and is attached to a side surface of the safety apparatus. | 03-26-2015 |
20150116238 | INFORMATION INTERACTION METHOD AND ELECTRONIC DEVICE - An information interaction method and an electronic device are provided. The method is applicable in a first electronic device. The first electronic device includes a first interaction unit and a second interaction unit, where the first interaction unit includes a first display unit. The method includes receiving device information of a second electronic device via the second interaction unit when the second interaction unit is in a working state; processing the device information of the second electronic device; and sending a procedure of the processing to the first interaction unit via the second interaction unit for displaying via the first display unit. When the second interaction unit is in a working state, the second interaction unit receives device information of the second electronic device, and the connection with the second electronic device may be achieved without inputting information manually, therefore the connection process is simple. | 04-30-2015 |
20150116241 | DATA DISPLAY METHOD AND ELECTRONIC DEVICE THEREOF - A data display method and an electronic device thereof are provided by the invention to address the technical problem in the prior art of the low security for displaying data due to the indistinguishable data display of the electronic device. The method is applied in an electronic device. The electronic device comprises a display unit and a touch unit. The electronic device is able to communicate data with an electronic accessory and there are public data and private data corresponding to the electronic accessory. The method comprises steps of verifying the electronic accessory when the electronic accessory has been attached on the surface of the touch unit; controlling the display unit to display both the public data and the private data if the verification is successful; and controlling the display unit to display only the public data if the verification is not successful. | 04-30-2015 |
Patent application number | Description | Published |
20110223311 | COTTONSEED OIL AND USES - The present specification relates to the production of cotton plants and seeds and oil prepared therefrom having elevated levels of oleic and reduced levels of palmitic and linoleic acids. Furthermore, cottonseeds having low levels of cyclopropane and/or cyclopropene fatty acids and/or reduced levels of gossypol are described herein. The specification also describe FatB and CPA-FAS nucleotide and amino acid sequences derived from cotton facilitating, inter alia the direct modification of plant oil content and/or composition. | 09-15-2011 |
20110229623 | VEGETABLE OILS AND USES THEREFOR - The specification relates to plants and their seeds and oil obtained therefrom, and to methods of producing same comprising oil having modified fatty acid compositions, such that 28% to 80% of the total fatty acid content in the seedoil is palmitic acid, 0% to 16% is palmitoleic acid, 0% to 4% is C16:2 fatty acid, 3% to 33% is stearic acid, 1% to 40% is oleic acid, 4% to 50% is linoleic acid and 0% to 10% is linolenic acid. The specification describes nucleic acid molecules encoding RNA capable of conferring these properties, in particular, RNA that inhibits expression of an oil biosynthesis gene encoding KASII in seeds of a plant. Genetic constructs and cells comprising the nucleic acid molecules are also described and claimed. | 09-22-2011 |
20130164798 | PROCESSES FOR PRODUCING HYDROCARBON PRODUCTS - The present invention relates to processes for producing industrial products such as hydrocarbon products from non-polar lipids in a vegetative plant part. Preferred industrial products include alkyl esters which may be blended with petroleum based fuels. | 06-27-2013 |
20130247451 | PROCESSES FOR PRODUCING LIPIDS - The present invention relates to processes for extracting lipid from vegetative plant parts such as leaves, stems, roots and tubers, and for producing industrial products such as hydrocarbon products from the lipids. Preferred industrial products include alkyl esters which may be blended with petroleum based fuels. | 09-26-2013 |
20130288318 | HIGH OLEIC ACID OILS - The present invention relates to extracted lipid with high levels, for example 90% to 95% by weight, oleic acid. The present invention also provides genetically modified plants, particularly oilseeds such as safflower, which can used to produce the lipid. Furthermore, provided are methods for genotyping and selecting plants which can be used to produce the lipid. | 10-31-2013 |
20140256006 | PROCESSES FOR PRODUCING HYDROCARBON PRODUCTS - The present invention relates to processes for producing industrial products such as hydrocarbon products from non-polar lipids in a vegetative plant part. Preferred industrial products include alkyl esters which may be blended with petroleum based fuels. | 09-11-2014 |
20150018571 | ENZYMES AND METHODS FOR PRODUCING OMEGA-3 FATTY ACIDS - The present invention relates generally to the field of recombinant fatty acid synthesis, particularly in transgenic plants. The application describes genes involved in fatty acid synthesis and provides methods and vectors for the manipulation of fatty acid composition of plant oils. In particular, the invention provides constructs for achieving the integration of multiple heterologous genes involved in fatty acid synthesis into the plant genome, such that the resulting plants produce altered levels of polyunsaturated fatty acids. Also described are methods for enhancing the expression of fatty acid biosynthesis enzymes by co-expressing a silencing suppressor within the plant storage organ. | 01-15-2015 |
20150037457 | PROCESSES FOR PRODUCING LIPIDS - The present invention relates to processes for extracting lipid from vegetative plant parts such as leaves, stems, roots and tubers, and for producing industrial products such as hydrocarbon products from the lipids. Preferred industrial products include alkyl esters which may be blended with petroleum based fuels. | 02-05-2015 |
20150176017 | VEGETABLE OILS AND USES THEREFOR - The specification relates to plants and their seeds and oil obtained therefrom, and to methods of producing same comprising oil having modified fatty acid compositions, such that 28% to 80% of the total fatty acid content in the seedoil is palmitic acid, 0% to 16% is palmitoleic acid, 0% to 4% is C16:2 fatty acid, 3% to 33% is stearic acid, 1% to 40% is oleic acid, 4% to 50% is linoleic acid and 0% to 10% is linolenic acid. The specification describes nucleic acid molecules encoding RNA capable of conferring these properties, in particular, RNA that inhibits expression of an oil biosynthesis gene encoding KASII in seeds of a plant. Genetic constructs and cells comprising the nucleic acid molecules are also described and claimed. | 06-25-2015 |
20150267216 | PROCESSES FOR PRODUCING HYDROCARBON PRODUCTS - The present invention relates to processes for producing industrial products such as hydrocarbon products from non-polar lipids in a vegetative plant part. Preferred industrial products include alkyl esters which may be blended with petroleum based fuels. | 09-24-2015 |
20150353863 | METHODS OF PRODUCING LIPIDS - The present invention relates to methods of producing lipids. In particular, the present invention relates to methods of increasing the level of one or more non-polar lipids and/or the total non-polar lipid content in a transgenic organism or part thereof. In one particular embodiment, the present invention relates to the use of an acyltransferase, for example, a monoacylglycerol acyltransferase (MGAT) to increase the level of one or more non-polar lipids and/or the total non-polar lipid content in plants, plant seed and/or leaves, algae and fungi. | 12-10-2015 |
20160002566 | PROCESSES FOR PRODUCING INDUSTRIAL PRODUCTS FROM PLANT LIPIDS - The present invention relates to methods of producing industrial products from plant lipids, particularly from vegetative parts of plants. In particular, the present invention provides oil products such as biodiesel and synthetic diesel and processes for producing these, as well as plants having an increased level of one or more non-polar lipids such as triacylglycerols and an increased total non-polar lipid content. In one particular embodiment, the present invention relates to combinations of modifications in two or more of lipid handling enzymes, oil body proteins, decreased lipid catabolic enzymes and/or transcription factors regulating lipid biosynthesis to increase the level of one or more non-polar lipids and/or the total non-polar lipid content and/or mono-unsaturated fatty acid content in plants or any part thereof. In an embodiment, the present invention relates to a process for extracting lipids. In another embodiment, the lipid is converted to one or more hydrocarbon products in harvested plant vegetative parts to produce alkyl esters of the fatty acids which are suitable for use as a renewable biodiesel fuel. | 01-07-2016 |
Patent application number | Description | Published |
20120142121 | HYDROCHLORIC ACID ETCH AND LOW TEMPERATURE EPITAXY IN A SINGLE CHAMBER FOR RAISED SOURCE-DRAIN FABRICATION - A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions. | 06-07-2012 |
20120146175 | INSULATING REGION FOR A SEMICONDUCTOR SUBSTRATE - An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride. | 06-14-2012 |
20120156847 | LAYER FORMATION WITH REDUCED CHANNEL LOSS - Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process. | 06-21-2012 |
20130193494 | TRANSISTOR WITH COUNTER-ELECTRODE CONNECTION AMALGAMATED WITH THE SOURCE/DRAIN CONTACT - The field effect device includes an active area made from semi-conducting material and a gate electrode separated from the active area by a dielectric gate material. A counter-electrode is separated from the active area by a layer of electrically insulating material. Two source/drain contacts are arranged on the active area on each side of the gate electrode. One of the source/drain contacts is made from a single material, overspills from the active area and connects the active area with the counter-electrode. The counter-electrode contact is delineated by a closed peripheral insulating pattern. | 08-01-2013 |
20130193514 | METHOD TO ENABLE THE FORMATION OF SILICON GERMANIUM CHANNEL OF FDSOI DEVICES FOR PFET THRESHOLD VOLTAGE ENGINEERING - An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks. | 08-01-2013 |
20130277747 | TRANSISTOR HAVING A STRESSED BODY - An embodiment of a transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel. | 10-24-2013 |
20130334651 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 12-19-2013 |
20140054698 | ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM NITRIDE LINER AND UPPER OXIDE LINER AND RELATED METHODS - An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers. | 02-27-2014 |
20140054699 | ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM OXIDE LINER AND UPPER NITRIDE LINER AND RELATED METHODS - An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers. | 02-27-2014 |
20140054706 | MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS - A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof. | 02-27-2014 |
20140054715 | SEMICONDUCTOR DEVICE WITH AN INCLINED SOURCE/DRAIN AND ASSOCIATED METHODS - A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface. | 02-27-2014 |
20140084372 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 03-27-2014 |
20140099769 | METHOD TO PROTECT AGAINST CONTACT RELATED SHORTS ON UTBB - Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches. | 04-10-2014 |
20140099773 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 04-10-2014 |
20140151759 | FACET-FREE STRAINED SILICON TRANSISTOR - The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended. | 06-05-2014 |
20140170834 | METHOD FOR MANUFACTURING A HYBRID SOI/BULK SEMICONDUCTOR WAFER - A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings. | 06-19-2014 |
20140210010 | METHOD TO FORM FINFET/TRIGATE DEVICES ON BULK SEMICONDUCTOR WAFERS - A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices. | 07-31-2014 |
20140239395 | CONTACT RESISTANCE REDUCTION IN FINFETS - A method for forming contacts in a semiconductor device includes forming a plurality of substantially parallel semiconductor fins on a dielectric layer of a substrate having a gate structure formed transversely to a longitudinal axis of the fins. The fins are merged by epitaxially growing a crystalline material between the fins. A field dielectric layer is deposited over the fins and the crystalline material. Trenches that run transversely to the longitudinal axis of the fins are formed to expose the fins in the trenches. An interface layer is formed over portions of the fins exposed in the trenches. Contact lines are formed in the trenches that contact a top surface of the interface layer on the fins and at least a portion of side surfaces of the interface layer on the fins. | 08-28-2014 |
20140239415 | STRESS MEMORIZATION IN RMG FINFETS - Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate dielectric; depositing a stressor over the channel region of the transistor structure, wherein the stressor provides a stress to the channel region; removing the stressor metal after the stress is memorized within the channel region; and depositing a work function metal over the channel region of the transistor structure, where the work function metal applies less stress to the channel region than the stress applied by the stressor. A transistor with memorized stress includes a source and drain region on a substrate; a stress-memorized channel region on the substrate that retains an externally applied stress; and a gate structure including a work function gate metal that applies less stress to the stress-memorized channel region than the externally applied stress. | 08-28-2014 |
20140291749 | MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS AND RELATED METHODS - A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer. | 10-02-2014 |
20140291750 | MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS WITH FIRST AND SECOND DIELECTRIC LAYERS AND RELATED METHODS - A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer. | 10-02-2014 |
20140302661 | CONTACT ISOLATION SCHEME FOR THIN BURIED OXIDE SUBSTRATE DEVICES - A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material. | 10-09-2014 |
20140312423 | SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS - A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided. | 10-23-2014 |
20140312461 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 10-23-2014 |
20140345517 | METHOD FOR THE FORMATION OF NANO-SCALE ON-CHIP OPTICAL WAVEGUIDE STRUCTURES - A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel. | 11-27-2014 |
20140353717 | SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON REGION - An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate. | 12-04-2014 |
20140353718 | SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON-GERMANIUM REGION - An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region. | 12-04-2014 |
20140353753 | FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED OVERLAP CAPACITANCE AND ENHANCED MECHANICAL STABILITY - Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET. | 12-04-2014 |
20140353760 | METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES - A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level. | 12-04-2014 |
20140353767 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate. | 12-04-2014 |
20140357039 | METHOD FOR THE FORMATION OF A PROTECTIVE DUAL LINER FOR A SHALLOW TRENCH ISOLATION STRUCTURE - On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers. | 12-04-2014 |
20140357060 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type. | 12-04-2014 |
20150093861 | METHOD FOR THE FORMATION OF CMOS TRANSISTORS - An SOI substrate includes first and second active regions separated by STI structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks. An oxide layer and nitride layer are then deposited. Using a mask, the nitride layer over the first active region is removed, and the mask and oxide layer are removed to expose the SOI substrate in the first active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the first active region and a protective nitride layer is deposited. The masking, nitride layer removal, and oxide layer removal steps are then repeated to expose the SOI in the second active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the second active region. | 04-02-2015 |
20150097212 | SEMICONDUCTOR DEVICE WITH RELAXATION REDUCTION LINER AND ASSOCIATED METHODS - A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed. | 04-09-2015 |
20150097244 | SEMICONDUCTOR DEVICE WITH A BURIED OXIDE STACK FOR DUAL CHANNEL REGIONS AND ASSOCIATED METHODS - A method for making a semiconductor device includes forming a buried oxide stack on a semiconductor wafer. The buried oxide stack includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. A semiconductor layer is formed on the second oxide layer. First and second channel regions are formed in the semiconductor layer. | 04-09-2015 |
20150099334 | METHOD OF MAKING A CMOS SEMICONDUCTOR DEVICE USING A STRESSED SILICON-ON-INSULATOR (SOI) WAFER - A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region. | 04-09-2015 |
20150099335 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING TRENCH ISOLATION REGIONS TO MAINTAIN CHANNEL STRESS - A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region. | 04-09-2015 |
20150102410 | SEMICONDUCTOR DEVICE INCLUDING STRESS LAYER ADJACENT CHANNEL AND RELATED METHODS - A method for making a semiconductor device may include forming a gate on a semiconductor layer, forming sidewall spacers adjacent the gate, and forming raised source and drain regions defining a channel in the semiconductor layer under the gate. The raised source and drain regions may be spaced apart from the gate by the sidewall spacers. The method may further include removing the sidewall spacers to expose the semiconductor layer between the raised source and drain regions and the gate, and forming a stress layer overlying the gate and the raised source and drain regions. The stress layer may contact the semiconductor layer between the raised source and drain regions and the gate. | 04-16-2015 |
20150102412 | SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE AND RELATED METHODS FOR MAKING SAME USING NON-OXIDIZING THERMAL TREATMENT - A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer. | 04-16-2015 |
20150108573 | SEMICONDUCTOR DEVICE INCLUDING VERTICALLY SPACED SEMICONDUCTOR CHANNEL STRUCTURES AND RELATED METHODS - A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures. | 04-23-2015 |
20150115370 | SEMICONDUCTOR DEVICE PROVIDING ENHANCED FIN ISOLATION AND RELATED METHODS - A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin. | 04-30-2015 |
20150179453 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 06-25-2015 |
20150187881 | CONTACT RESISTANCE REDUCTION IN FINFETS - A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins. | 07-02-2015 |
20150194496 | CONTACT RESISTANCE REDUCTION IN FINFETS - A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins. | 07-09-2015 |
20150200205 | SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS - A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided. | 07-16-2015 |
20150279861 | DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES - Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material. | 10-01-2015 |
20150287648 | FINFET INCLUDING TUNABLE FIN HEIGHT AND TUNABLE FIN WIDTH RATIO - A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material. | 10-08-2015 |
20160035843 | CMOS IN SITU DOPED FLOW WITH INDEPENDENTLY TUNABLE SPACER THICKNESS - A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions. | 02-04-2016 |
Patent application number | Description | Published |
20140299880 | LAYER FORMATION WITH REDUCED CHANNEL LOSS - Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process. | 10-09-2014 |
20140377923 | METHOD TO FORM FINFET/TRIGATE DEVICES ON BULK SEMICONDUCTOR WAFERS - A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices. | 12-25-2014 |
20150126003 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made on the bottom portion to produce a silicon-germanium region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type. | 05-07-2015 |
20150206972 | METHOD OF MAKING A CMOS SEMICONDUCTOR DEVICE USING A STRESSED SILICON-ON-INSULATOR (SOI) WAFER - A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region. | 07-23-2015 |
20150243660 | CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD - A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide. | 08-27-2015 |
20150303285 | MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS - A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof. | 10-22-2015 |
20150325487 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate. | 11-12-2015 |
20150333086 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH DIFFERENT FIN SETS - A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions. | 11-19-2015 |
20150333155 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES - A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions. | 11-19-2015 |
20150349085 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWALL SPACERS FOR CONFINING EPITAXIAL GROWTH - A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers. | 12-03-2015 |
20150357243 | METHOD FOR MAKING STRAINED SEMICONDUCTOR DEVICE AND RELATED METHODS - A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states. | 12-10-2015 |
20150357425 | BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME - An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions. | 12-10-2015 |
20150357439 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH ISOLATION PILLARS BETWEEN ADJACENT SEMICONDUCTOR FINS - A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins. | 12-10-2015 |
20150357441 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE WHILE AVOIDING NODULES ON A GATE - A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins. | 12-10-2015 |
20150364578 | METHOD OF FORMING A REDUCED RESISTANCE FIN STRUCTURE - Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions. | 12-17-2015 |
20150372104 | MULTI-CHANNEL GATE-ALL-AROUND FET - A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs. | 12-24-2015 |
20150372107 | SEMICONDUCTOR DEVICES HAVING FINS, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FINS - Methods and structures associated with forming finFETs that have fin pitches less than 30 nm are described. A selective nitridation process may be used during spacer formation on the gate to enable finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions. | 12-24-2015 |
20150372140 | FINFETS HAVING STRAINED CHANNELS, AND METHODS OF FABRICATING FINFETS HAVING STRAINED CHANNELS - Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET. | 12-24-2015 |
20150380258 | METHOD FOR CONTROLLING HEIGHT OF A FIN STRUCTURE - Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights. | 12-31-2015 |
20160043177 | SEMICONDUCTOR DEVICE WITH THINNED CHANNEL REGION AND RELATED METHODS - A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers. | 02-11-2016 |
20160049402 | SEMICONDUCTOR DEVICE HAVING FINS WITH IN-SITU DOPED, PUNCH-THROUGH STOPPER LAYER AND RELATED METHODS - A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region. | 02-18-2016 |
20160104644 | PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE - Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode. | 04-14-2016 |