Prathiba
Prathiba Kumar, Nadu IN
Patent application number | Description | Published |
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20120278594 | PERFORMANCE BOTTLENECK IDENTIFICATION TOOL - A computer program product for identifying bottlenecks includes a computer readable storage medium with stored computer readable program instructions. The computer readable program instructions, when executed, provide a data collector module, a mapper module, and an analyzer module that are collectively configured to read mapped data and configuration files, and identify, based upon the mapped data and the configuration files, an undesirable bottleneck condition that causes a computer program to run inefficiently. A method includes reading a configuration file that includes data regarding processor components, and collecting data from hardware activity counters based upon the configuration file. The method also includes mapping the collected data to corresponding sections of code of a computer program, reading the mapped data and the configuration file, and identifying, based upon the reading of the mapped data and the configuration file, an undesirable bottleneck condition that causes the processor to run the computer program inefficiently. | 11-01-2012 |
Prathiba Kumar, Udumalpet IN
Patent application number | Description | Published |
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20120324208 | Effective Validation of Execution Units Within a Processor - A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated. | 12-20-2012 |
20130117588 | Run-Time Task-Level Dynamic Energy Management - A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator. | 05-09-2013 |
20140059383 | Effective Validation of Execution Units Within a Processor - A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated. | 02-27-2014 |
20140075219 | Run-Time Task-Level Dynamic Energy Management - A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator. | 03-13-2014 |
Prathiba Kumar, Tamil Nadu IN
Patent application number | Description | Published |
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20140173222 | Validating Cache Coherency Protocol Within a Processor - A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated. | 06-19-2014 |