| Patent application number | Description | Published |
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| 20130309837 | PREVENTING SHORTING OF ADJACENT DEVICES - Embodiments of the present invention provide a method of preventing electrical shorting of adjacent semiconductor devices. The method includes forming a plurality of fins of a plurality of field-effect-transistors on a substrate; forming at least one barrier structure between a first and a second fin of the plurality of fins; and growing an epitaxial film from the plurality of fins, the epitaxial film extending horizontally from sidewalls of at least the first and second fins and reaching the barrier structure situating between the first and second fins. | 11-21-2013 |
| 20140070285 | METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES - One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity. | 03-13-2014 |
| 20140124862 | STRUCTURE AND METHOD TO IMPROVE ETSOI MOSFETS WITH BACK GATE - A structure to improve ETSOI MOSFET devices includes a wafer having regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in the hole. | 05-08-2014 |
| 20140134836 | DIELECTRIC CAP LAYER FOR REPLACEMENT GATE WITH SELF-ALIGNED CONTACT - Embodiments of the present invention provide a method of forming borderless contact for transistors. The method includes forming a sacrificial gate structure embedded in a first dielectric layer, the sacrificial gate structure including a sacrificial gate and a second dielectric layer surrounding a top and sidewalls of the sacrificial gate; removing a portion of the second dielectric layer that is above a top level of the sacrificial gate to create a first opening surrounded directly by the first dielectric layer; removing the sacrificial gate exposed by the removing of the portion of the second dielectric layer to create a second opening surrounded by a remaining portion of the second dielectric layer; filling the second opening with one or more conductive materials to form a gate of a transistor; and filling the first opening with a layer of dielectric material to form a dielectric cap of the gate of the transistor. | 05-15-2014 |
| 20140138775 | DUAL EPI CMOS INTEGRATION FOR PLANAR SUBSTRATES - Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures. | 05-22-2014 |
| 20140191319 | FINFET COMPATIBLE DIODE FOR ESD PROTECTION - A diode for integration with finFET devices is disclosed. An in-situ doped epitaxial silicon region is grown on the cathode or anode of the diode to increase the surface area of the junction and overall silicon volume for improved heat dissipation during an ESD event. | 07-10-2014 |
| 20140264486 | METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE - One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material. | 09-18-2014 |
| 20140264487 | METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE - One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material. | 09-18-2014 |
| 20140353732 | HALO REGION FORMATION BY EPITAXIAL GROWTH - A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device. | 12-04-2014 |
| 20140353753 | FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED OVERLAP CAPACITANCE AND ENHANCED MECHANICAL STABILITY - Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET. | 12-04-2014 |
| 20140353767 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate. | 12-04-2014 |
| 20150014772 | PATTERNING FINS AND PLANAR AREAS IN SILICON - A method including for forming a plurality of mandrels, a plurality of sidewall spacers, and a plurality of offset spacers above a hardmask layer, the sidewall spacers being separated by the plurality of mandrels and the plurality of offset spacers in an alternating order, each of the plurality of sidewall spacers being in direct contact with a single offset spacer and a single mandrel, the plurality of mandrels being separated from the plurality of offset spacers by the plurality of sidewall spacers, depositing a fill material above the plurality of mandrels, above the plurality of sidewall spacers, above the plurality of offset spacers, and above the hardmask layer, and removing the plurality of mandrels and the plurality of offset spacers selective to the plurality of sidewall spacers, the fill material, and the hardmask layer. | 01-15-2015 |
| 20150041869 | METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE - One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material. | 02-12-2015 |
| 20150064863 | MASKLESS DUAL SILICIDE CONTACT FORMATION - Embodiments of present invention provide a method of forming silicide contacts of transistors. The method includes forming a first set of epitaxial source/drain regions of a first set of transistors; forming a sacrificial epitaxial layer on top of the first set of epitaxial source/drain regions; forming a second set of epitaxial source/drain regions of a second set of transistors; converting a top portion of the second set of epitaxial source/drain regions into a metal silicide and the sacrificial epitaxial layer into a sacrificial silicide layer in a silicidation process wherein the first set of epitaxial source/drain regions underneath the sacrificial epitaxial layer is not affected by the silicidation process; removing selectively the sacrificial silicide layer; and converting a top portion of the first set of epitaxial source/drain regions into another metal silicide. | 03-05-2015 |
| 20150069532 | METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACT ELEMENTS USING A REPLACEMENT GATE PROCESS AND THE RESULTING DEVICES - One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of a plurality of source/drain regions and, with the replacement gate structure in position, forming at least one source/drain contact structure for each of the plurality of source/drain regions, wherein the at least one source/drain contact structure is conductively coupled to a portion of the metal silicide layer and a dimension of the at least one source/drain contact structure in a gate width direction of the transistor is less than a dimension of the source/drain region in the gate width direction. | 03-12-2015 |
