Patent application number | Description | Published |
20080229068 | ADAPTIVE FETCH GATING IN MULTITHREADED PROCESSORS, FETCH CONTROL AND METHOD OF CONTROLLING FETCHES - A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signals are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches. | 09-18-2008 |
20080229134 | RELIABILITY MORPH FOR A DUAL-CORE TRANSACTION-PROCESSING SYSTEM - In processors having buffers to manage instruction flow referred to as a ReOrder Buffer (ROB) it is shown that these buffers are of the same approximate size of a checkpoint array for architected state. In a particular “morphing mode” in which a pair of processors can be configured to provide different functionalities on demand, a new “High-Reliability” (HR) mode is provided in which the ROB of one of the processors is used for a checkpoint array, and the pair of processors is made to run in lockstep on a single instruction stream under the control of the remaining ROB so as to provide redundant, hence highly-reliable computing. | 09-18-2008 |
20080229145 | Method and system for soft error recovery during processor execution - A system for soft error recovery used during processor execution. The system may include a microprocessor, processor, controller, or the like. The system may also include a pipeline to reduce the cycle time of the processor, and a write-back stage within the pipeline. The system may further include an error-correcting code stage before the write-back stage that checks a value to be written by the processor for any error. The error-correcting code stage may correct any error in the value, and the pipeline may lack a recovery unit pipeline. | 09-18-2008 |
20080244186 | WRITE FILTER CACHE METHOD AND APPARATUS FOR PROTECTING THE MICROPROCESSOR CORE FROM SOFT ERRORS - A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints. | 10-02-2008 |
20080256345 | Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System - An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions. | 10-16-2008 |
20080256383 | METHOD AND SYSTEM OF PREDICTING MICROPROCESSOR LIFETIME - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 10-16-2008 |
20080281476 | METHODS FOR THERMAL MANAGEMENT OF THREE-DIMENSIONAL INTEGRATED CIRCUITS - A method of dynamic thermal management in a multi-dimensional integrated circuit or device is provided. The method includes monitoring on-chip temperatures, power dissipation, and performance of device layers. The method includes comparing on-chip temperatures to thermal thresholds, on-chip power dissipation to power thresholds and on-chip performance to performance thresholds. Also, the method includes analyzing interactions between temperatures, power, and performance of different device layers within the multi-dimensional integrated circuits. The method includes activating layer-specific thermal and power management within performance constraints on one or more device layers through actuators in the corresponding device layers, depending on the severity of heating. | 11-13-2008 |
20080313509 | METHOD AND APPARATUS FOR PREVENTING SOFT ERROR ACCUMULATION IN REGISTER ARRAYS - A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater than a threshold. | 12-18-2008 |
20090013207 | PREDICTING MICROPROCESSOR LIFETIME RELIABILITY USING ARCHITECTURE-LEVEL STRUCTURE-AWARE TECHNIQUES - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 01-08-2009 |
20090048808 | METHOD AND APPARATUS FOR MONITORING AND ENHANCING ON-CHIP MICROPROCESSOR RELIABILITY - A system and method for projecting reliability to manage system functions includes an activity module which determines activity in the system. A reliability module interacts with the activity module to determine a reliability measurement for the module in real-time based upon the activity and measured operational quantities of the system. A management module manages actions of the system based upon the reliability measurement input from the reliability module. This may be to provide corrective action, to reallocate resources, increase reliability of the module, etc. | 02-19-2009 |
20090049318 | METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT - A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally. | 02-19-2009 |
20090064164 | METHOD OF VIRTUALIZATION AND OS-LEVEL THERMAL MANAGEMENT AND MULTITHREADED PROCESSOR WITH VIRTUALIZATION AND OS-LEVEL THERMAL MANAGEMENT - A program product and method of managing task execution on an integrated circuit chip such as a chip-level multiprocessor (CMP) with Simultaneous MultiThreading (SMT). Multiple chip operating units or cores have chip sensors (temperature sensors or counters) for monitoring temperature in units. Task execution is monitored for hot tasks and especially for hotspots. Task execution is balanced, thermally, to minimize hot spots. Thermal balancing may include Simultaneous MultiThreading (SMT) heat balancing, chip-level multiprocessors (CMP) heat balancing, deferring execution of identified hot tasks, migrating identified hot tasks from a current core to a colder core, User-specified Core-hopping, and SMT hardware threading. | 03-05-2009 |
20090089602 | METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT - A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system. | 04-02-2009 |
20090144669 | METHOD AND ARRANGEMENT FOR ENHANCING PROCESS VARIABILITY AND LIFETIME RELIABILITY THROUGH 3D INTEGRATION - A method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an arrangement for implementing the inventive method. | 06-04-2009 |
20090144678 | METHOD AND ON-CHIP CONTROL APPARATUS FOR ENHANCING PROCESS RELIABILITY AND PROCESS VARIABILITY THROUGH 3D INTEGRATION - A method and on-chip controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. | 06-04-2009 |
20090177919 | DYNAMIC REDUNDANCY FOR MICROPROCESSOR COMPONENTS AND CIRCUITS PLACED IN NONOPERATIONAL MODES - An apparatus for implementing dynamic redundancy for a microprocessor system includes a plurality of microprocessor components, each of which is capable of being selectively placed in a non-operational mode while one or more other of the microprocessor components remain in an operational mode, and then subsequently restored from the non-operational mode back to the operational mode, the spare microprocessor component configured to be switched from the non-operational mode to the operational mode whenever one of the plurality of the microprocessor components is placed in the non-operational mode, and wherein the spare microprocessor component is configured to be switched back to the non-operational mode whenever each of the microprocessor components are in the operational mode; and multiplexing circuitry configured to map the use of the microprocessor components and the spare microprocessor component with respect to the operational mode and the non-operational mode. | 07-09-2009 |
20090199020 | METHOD AND SYSTEM OF MULTI-CORE MICROPROCESSOR POWER MANAGEMENT AND CONTROL VIA PER-CHIPLET, PROGRAMMABLE POWER MODES - A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels. | 08-06-2009 |
20090249349 | Power-Efficient Thread Priority Enablement - A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode. | 10-01-2009 |
20090328055 | SYSTEMS AND METHODS FOR THREAD ASSIGNMENT AND CORE TURN-OFF FOR INTEGRATED CIRCUIT ENERGY EFFICIENCY AND HIGH-PERFORMANCE - A system and method for improving efficiency of a multi-core architecture includes, in accordance with a workload, determining a number of cores to shut down based upon a metric that combines parameters to represent operational efficiency. Threads of the workload are reassigned to cores remaining active by assigning threads based on priority constraints and thread execution history to improve the operational efficiency of the multi-core architecture. | 12-31-2009 |
20100015732 | SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP - Base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet, which provides the same functionality as one of the at least one non-functional chiplet is designed to provide, is vertically stacked. The at least one repair semiconductor chiplet provides the functionality that the at least one non-functional chiplet is designed to provide to the base semiconductor chip. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. In case a first attempt to repair the base semiconductor chip by stacking repair semiconductor chips is unsuccessful, additional repair semiconductor chips may be subsequently stacked to fully repair the base semiconductor chip. | 01-21-2010 |
20100083203 | Modeling System-Level Effects of Soft Errors - Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile. | 04-01-2010 |
20100180081 | Adaptive Data Prefetch System and Method - A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds. | 07-15-2010 |
20100262808 | MANAGING INSTRUCTIONS FOR MORE EFFICIENT LOAD/STORE UNIT USAGE - The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit. | 10-14-2010 |
20100268930 | ON-CHIP POWER PROXY BASED ARCHITECTURE - The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value. | 10-21-2010 |
20100268975 | On-Chip Power Proxy Based Architecture - A method for estimating power consumption within a multi-core microprocessor chip is provided. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value. | 10-21-2010 |
20110040994 | Two-Level Guarded Predictive Power Gating - A mechanism is provided for two-level guarded predictive power gating of a set of units within the data processing system. A success determines whether a unit within the set of units is power gated during a monitoring interval. If the unit is power gated, the success monitor determines whether a count of idle cycles for the unit is below a breakeven point. If the count is above the breakeven point, the success monitor increments a success efficiency counter. If the count is below the breakeven point, the success monitor determines whether the unit needs to be woke up. If the unit needs to be woke up, the success monitor increments a harmful efficiency counter. If the value of the harmful efficiency counter is less than the value from the success efficiency counter, the success monitor enables power gating for the unit via a first-level power-gating mechanism. | 02-17-2011 |
20110040995 | Predictive Power Gating with Optional Guard Mechanism - A mechanism is provided for predictively power gating a set of units within the data processing system. A second-level power gating controller monitors a set of events for each unit in a set of units within the data processing system. The second-level power gating controller identifies idle sequences of a predetermined set of cycles within the events from each unit where the unit is idle. The second-level power gating controller determines preceding sequences of a predetermined length that precede the idle sequences. The second-level power gating controller determines an accuracy of the preceding sequences. Responsive to the accuracy being above a threshold, the second-level power gating controller sends a permit command to a first-level power gating mechanism associated with the unit to permit power gating of the unit. | 02-17-2011 |
20110191776 | LOW OVERHEAD DYNAMIC THERMAL MANAGEMENT IN MANY-CORE CLUSTER ARCHITECTURE - A semiconductor chip includes a plurality of multi-core clusters each including a plurality of cores and a cluster controller unit. Each cluster controller unit is configured to control thread assignment within the multi-core cluster to which it belongs. The cluster controller unit monitors various parameters measured in the plurality of cores within the multi-core cluster to estimate the computational demand of each thread that runs in the cores. The cluster controller unit may reassign the threads within the multi-core cluster based on the estimated computational demand of the threads and transmit a signal to an upper-level software manager that controls the thread assignment across the semiconductor chip. When an acceptable solution to thread assignment cannot be achieved by shuffling of threads within the multi-core cluster, the cluster controller unit may also report inability to solve thread assignment to the upper-level software manager to request a system level solution. | 08-04-2011 |
20120030481 | Measuring Data Switching Activity in a Microprocessor - A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity. | 02-02-2012 |
20120210328 | Guarded, Multi-Metric Resource Control for Safe and Efficient Microprocessor Management - A mechanism is provided for guarded, multi-metric resource control. Monitoring is performed for an intended action to address a negative condition from a resource manager in a plurality of resource managers in the data processing system. Responsive to receiving the intended action, a determination is made as to whether the intended action will cause an additional negative condition within the data processing system. Responsive to determining that the intended action will cause the additional negative condition within the data processing system, at least one alternative action is identified to be implemented in the data processing system that addresses the negative condition while not causing any additional negative condition. The at least one alternative action is then implemented in the data processing system. | 08-16-2012 |
20120245897 | Virtualized Abstraction with Built-in Data Alignment and Simultaneous Event Monitoring in Performance Counter Based Application Characterization and Tuning - Techniques for monitoring a set of one or more event counters of application execution are provided. The techniques include constructing a virtual performance monitoring counter (VPMC) layer as a unified abstraction of a physical performance monitoring counter (PMC) architecture, and incorporating one or more programming interfaces (PIs) in connection with the virtual performance monitoring counter, wherein the one or more programming interfaces facilitate simultaneous access and data monitoring across a set of one or more event counters. | 09-27-2012 |
20120260117 | Dynamically Tune Power Proxy Architectures - A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted. | 10-11-2012 |
20130046955 | Local Computation Logic Embedded in a Register File to Accelerate Programs - A system and methods for improving performance of an central processing unit. The central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into a one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays. | 02-21-2013 |
20130055185 | VERTICAL POWER BUDGETING AND SHIFTING FOR 3D INTEGRATION - A method is provided for managing power distribution on a 3D chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints. | 02-28-2013 |
20130096902 | Hardware Execution Driven Application Level Derating Calculation for Soft Error Rate Analysis - Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design. | 04-18-2013 |
20130311811 | Power Shifting in Multicore Platforms by Varying SMT Levels - Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted. | 11-21-2013 |
20130311812 | Power Shifting in Multicore Platforms by Varying SMT Levels - Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted. | 11-21-2013 |
20130339762 | ADAPTIVE WORKLOAD BASED OPTIMIZATIONS TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 12-19-2013 |
20140082574 | Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 03-20-2014 |
20140082580 | CURRENT-AWARE FLOORPLANNING TO OVERCOME CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 03-20-2014 |
20140143570 | THREAD CONSOLIDATION IN PROCESSOR CORES - According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores. | 05-22-2014 |
20140143783 | THREAD CONSOLIDATION IN PROCESSOR CORES - According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores. | 05-22-2014 |
20140148927 | DYNAMIC POWER DISTRIBUTION - According to one embodiment, a method for dynamically sharing power grids of a device includes providing power from a first power supply to a first power grid in a first component of the device. The method also includes providing power from a second power supply to a second power grid in a second component of the device and dynamically changing, by a controller, a state of a first switch that controls a sharing of power between the first power grid and the second power grid during a runtime of the device. | 05-29-2014 |
20140148961 | DYNAMIC POWER DISTRIBUTION - According to one embodiment, a method for dynamically sharing power grids of a device includes providing power from a first power supply to a first power grid in a first component of the device. The method also includes providing power from a second power supply to a second power grid in a second component of the device and dynamically changing, by a controller, a state of a first switch that controls a sharing of power between the first power grid and the second power grid during a runtime of the device. | 05-29-2014 |
20140159803 | SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP - In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. | 06-12-2014 |
20140195996 | ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 07-10-2014 |
20140281605 | POWER MANAGEMENT FOR A COMPUTER SYSTEM - Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section. | 09-18-2014 |
20140281629 | POWER MANAGEMENT FOR A COMPUTER SYSTEM - Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section. | 09-18-2014 |
20150074356 | PROCESSOR WITH MEMORY-EMBEDDED PIPELINE FOR TABLE-DRIVEN COMPUTATION - A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction. | 03-12-2015 |
20150074381 | PROCESSOR WITH MEMORY-EMBEDDED PIPELINE FOR TABLE-DRIVEN COMPUTATION - A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction. | 03-12-2015 |
20150076908 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 03-19-2015 |
20150077170 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 03-19-2015 |
20150081123 | PREDICTIVELY TURNING OFF A CHARGE PUMP SUPPLYING VOLTAGE FOR OVERDRIVING GATES OF THE POWER SWITCH HEADER IN A MICROPROCESSOR WITH POWER GATING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit. | 03-19-2015 |
20150081125 | PREDICTIVELY TURNING OFF A CHARGE PUMP SUPPLYING VOLTAGE FOR OVERDRIVING GATES OF THE POWER SWITCH HEADER IN A MICROPROCESSOR WITH POWER GATING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit. | 03-19-2015 |
20150082065 | ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES - A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source. | 03-19-2015 |
20150082066 | ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request. | 03-19-2015 |
20150082069 | ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES - A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source. | 03-19-2015 |
20150082070 | ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request. | 03-19-2015 |