Poulton, US
Jason Poulton, Akron, OH US
Patent application number | Description | Published |
---|---|---|
20090105423 | Method for preparing low molecular weight polymers - A process for producing low molecular weight polymers, the process comprising partially hydrogenating an unsaturated polymer to form a partially hydrogenated polymer, and reacting the partially hydrogenated polymer with an acyclic alkene in the presence of a metathesis catalyst. | 04-23-2009 |
20120010355 | POLYHEDRAL-MODIFIED POLYMER - A macromolecule including a polymer and a polyhedral radical chemically bonded to a terminus of the polymer provides numerous processing and performance advantages. Further functionalization of this macromolecule also is described as being advantageous in certain circumstances. Methods of providing, functionalizing, and utilizing the macromolecule also are provided. | 01-12-2012 |
Jason Poulton US
Patent application number | Description | Published |
---|---|---|
20130041096 | POLYHEDRAL-MODIFIED POLYMER - A macromolecule including a polymer and a polyhedral radical chemically bonded to a terminus of the polymer provides numerous processing and performance advantages. Further functionalization of this macromolecule also is described as being advantageous in certain circumstances. Methods of providing, functionalizing, and utilizing the macro-molecule also are provided. | 02-14-2013 |
Jason T. Poulton, Stow, OH US
Patent application number | Description | Published |
---|---|---|
20110184137 | CATALYSTS FOR PREPARING CIS 1,4-POLYDIENES - A polymerization catalyst composition for preparing cis 1,4-polydienes is provided. The catalyst composition comprises (a) a metal-containing compound, said metal being a transition metal or a lanthanide metal; (b) a carbene, (c) an alkylating agent, and optionally (d) a halogen-containing compound with the proviso that the halogen-containing compound must be present when none of the metal-containing compound and the alkylating agent contain a labile halogen atom. Also provided is a process for producing a polydiene comprising reacting a conjugated diene in the presence of the polymerization catalyst composition. | 07-28-2011 |
20110263794 | New Polymers And Use Thereof In Preparation Of High Impact Polymeric Compositions - Terminally functionalized polymers that are living or pseudo-living polymers reacted with certain allyl glycidyl ethers, or certain allylhalosilanes or combinations thereof, and a process for preparing the terminally functionalized polymers. Rubber-modified polymeric compositions comprising the terminally functionalized polymers. | 10-27-2011 |
20120172553 | Process For Producing Polydienes - A process for preparing a polydiene, the process comprising the step of polymerizing conjugated diene monomer in the presence of a dihydrocarbyl ether, where said step of polymerizing takes place within a polymerization mixture that includes less than 20% by weight of organic solvent based on the total weight of the polymerization mixture, and where said step of polymerizing employs a lanthanide-based catalyst system that includes the combination of or reaction product of ingredients including (a) a lanthanide compound, (b) an aluminoxane, (c) an organoaluminum compound other than an aluminoxane, and (d) a bromine-containing compound selected from the group consisting of elemental bromine, bromine-containing mixed halogens, and organic bromides. | 07-05-2012 |
John Poulton, Chapel Hill, NC US
Patent application number | Description | Published |
---|---|---|
20090129505 | PARTIAL-RATE TRANSFER MODE FOR FIXED-CLOCK-RATE INTERFACE - Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter. | 05-21-2009 |
20100220828 | EDGE-BASED SAMPLER OFFSET CORRECTION - Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler ( | 09-02-2010 |
20120243632 | PARTIAL-RATE TRANSFER MODE FOR FIXED-CLOCK-RATE INTERFACE - Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter. | 09-27-2012 |
John E. Poulton, Chapel Hill, NC US
Patent application number | Description | Published |
---|---|---|
20160064066 | MAINTENANCE OPERATIONS IN A DRAM - A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order. | 03-03-2016 |
John W. Poulton, Chapel, NC US
Patent application number | Description | Published |
---|---|---|
20140301134 | GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT - A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network. | 10-09-2014 |
John Wood Poulton, Chapel Hill, NC US
Patent application number | Description | Published |
---|---|---|
20100027712 | EQUALIZING TRANSMITTER AND METHOD OF OPERATION - A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel. | 02-04-2010 |
20110025385 | Power Supply Noise Rejection in PLL or DLL Circuits - A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency lock. | 02-03-2011 |
20120057260 | Power Supply Shunt - A power supply shunt for an electronic circuit. The power supply shunt includes at least two Field Effect Transistors (FETs), a first of the FETs having its drain coupled to a terminal of an electronic circuit and its source coupled to another of the FETs, and a second of the FETs having its source coupled to ground and its drain coupled to another of the FETs. The first FET has a bulk terminal that floats with respect to ground. | 03-08-2012 |
20160087819 | EQUALIZING TRANSMITTER AND METHOD OF OPERATION - A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel. | 03-24-2016 |
Kenneth D. Poulton, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20080238747 | SUB-HARMONIC IMAGE MITIGATION IN DIGITAL-TO-ANALOG CONVERSION SYSTEMS - A digital-to-analog conversion system comprises a digital input, a digital-to-analog converter and a modified digital signal generator. The digital-to-analog converter has a conversion frequency and is subject to a periodic error having a periodicity equal to that of an N-th sub-harmonic of the conversion frequency, where N is an integer. The digital input is operable to receive a digital input signal. The modified digital signal generator is interposed between the digital input and the digital-to-analog converter and is operable in response to the digital input signal to generate a modified digital signal. The modified digital signal comprises a dynamic digital mitigation component that mitigates the periodic error of the digital-to-analog converter. | 10-02-2008 |
20080266157 | STAGGERED INTERLEAVED NYQUIST REGIONS AVOID GUARD BAND INDUCED HOLES WHEN SAMPLING A BAND LIMITED SIGNAL - Staggered interleaved Nyquist regions associated with differing ADC clock rates (F | 10-30-2008 |
20080266163 | Analog-to-Digital Converter with Reduced Metastable Errors - In an analog-to-digital converter, an analog-to-digital conversion stage comprising a comparator and an analog residual signal generator. The comparator is operable to compare an analog input signal or a sample of the analog input signal with a threshold to generate a bit signal. The analog residual signal generator is operable to generate an analog residual signal from signals comprising the sample of the analog input signal and the bit signal. The analog residual signal generator comprises a summing element, a selective inverter and an amplifier in series. The summing element is operable to sum a signal input to it with a reference signal. The selective inverter precedes the summing element, and is operable in response to a first state of the bit signal to pass a signal input to it, and is operable in response to a second state of the bit signal to invert the signal input to it. | 10-30-2008 |