Po-Hung
Po-Hung Chen, Hsinchu TW
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20080238439 | Methods of testing fuse elements for memory devices - A method of testing a fuse element for a memory device is provided. A first test probe is electrically connected to a program terminal of the memory device. A second test probe is electrically connected to a ground terminal. The fuse element is on an electrical circuit path between the program terminal and the ground terminal. The first and second test probes are electrically connected to a testing device. A first voltage is applied with the testing device between the program terminal and the ground terminal. At least part of a first current of the first voltage flows across the fuse element. The first voltage and the at least part of the first current that flows across the fuse element is not large enough to change the conductivity state of the fuse element. The first current is measured and used to evaluated the conductive state of the fuse element. | 10-02-2008 |
Po-Hung Chen, Hsin-Chu TW
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20100066944 | Display Device with Low Scratch Visibility and Manufacturing Method Thereof - A display device and a manufacturing method thereof are provided. The display device includes a light guide, a light source, and a brightness enhancement film (BEF), and a dual brightness enhancement film (DBEF). The light guide has a first edge along a first direction and a second edge adjacent to the first edge corresponding to the light source. The BEF is disposed on the light guide and has a plurality of prisms along a second direction which rotates from 0 to 90 degrees with respect to the first direction. The DBEF has a transmission axis along a third direction which also rotates from 0 to 90 degrees with respect to the first direction. | 03-18-2010 |
20130107571 | DISPLAY APPARATUS | 05-02-2013 |
20130208509 | Backlight Module and Thermal Design Thereof - A backlight module includes a light guide plate, a light source module, a supporting frame, and a heat conductive glue layer. The light guide plate has a light-entering end; the light source module is disposed corresponding to the light-entering end and includes a flexible circuit board and a plurality of light sources. The flexible circuit board extends along the light-entering end and has a light source-bearing area and a heat-dissipating area, wherein a width of the heat-dissipating area in a direction perpendicular to the light-entering end is not smaller than a width of the light source-bearing area. The plurality of light sources are disposed in the light source-bearing area. The supporting frame has a holding portion which is bent to form an accommodation space for accommodating the light source module and the light-entering end. The heat conductive glue layer is disposed between the heat-dissipating area and an inner side of the holding portion for conducting heat from the heat-dissipating area to the holding portion. | 08-15-2013 |
20140232967 | DISPLAY MODULE - A display module includes a panel frame, a display panel, a system frame, and a printed circuit board. The panel frame includes a baseplate having at least one edge, at least one sidewall located on the edge, at least one top wall adjacent to the sidewall, and a support element. An accommodating space is formed by the sidewall and the baseplate. The support element includes a first support portion and a second support portion connected to the first support portion. The support element extends from the edge of the baseplate toward the outside of the accommodating space. The display panel is disposed on the panel frame. The first support portion is disposed on the system frame. The printed circuit board is disposed on the second support portion. | 08-21-2014 |
Po-Hung Chen, Taoyuan Hsien TW
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20140118983 | ASSEMBLING STRUCTURE OF INVERTER AND GROUND WIRE - An assembling structure includes a ground wire, an inverter, a first fixing element, and a clamping device. The inverter includes a casing. The clamping device is disposed on the casing. The clamping device includes a first end, a second end, and a pressing part between the first end and the second end. The second end of the clamping device is previously fixed on the casing. After the ground wire is transferred through an entrance between the first end of the clamping device and the casing, the ground wire is clamped between the pressing part and the casing. Afterwards, by using the fixing element, the first end of the clamping device is fixed on the casing, the ground wire is fixed on the casing by the pressing part of the clamping device, and the inverter is fixed on the rack simultaneously. | 05-01-2014 |
Po-Hung Chen, Taipei City TW
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20090141573 | System and Method for Better Testability of OTP Memory - A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory. | 06-04-2009 |
20100325364 | CACHE CONTROLLER, METHOD FOR CONTROLLING THE CACHE CONTROLLER, AND COMPUTING SYSTEM COMPRISING THE SAME - A cache controller, a method for controlling the cache controller, and a computing system comprising the same are provided. The computer system comprises a processor and a cache controller. The cache controller is electrically connected to the processor and comprises a first port, a second port, and at least one cache. The first port is configured to receive an address of a content, wherein a type of the content is one of instruction and data. The second port is configured to receive an information bit corresponding to the content, wherein the information bit indicates the type of the content. The at least one cache comprises at least one cache lines. Each of the cache lines comprises a content field and corresponding to an information field. The content and the information bit is stored in the content field of one of the cache lines and the corresponding information field respectively according to the information bit and the address. Thereby, instruction and data are separated in a unified cache. | 12-23-2010 |
20100329055 | MEASURING ELECTRICAL RESISTANCE - A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device. | 12-30-2010 |
20110273949 | ELECTRICAL FUSE PROGRAMMING TIME CONTROL SCHEME - A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse. | 11-10-2011 |
20120057423 | ELECTRICAL FUSE MEMORY ARRAYS - Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column. | 03-08-2012 |
20120081165 | HIGH VOLTAGE TOLERATIVE DRIVER - A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS. | 04-05-2012 |
20120086495 | VOLTAGE LEVEL SHIFTER - An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node. | 04-12-2012 |
20130097340 | USB MULTI-FUNCTIONS DEVICE AND METHOD THEREOF - A USB multi-functions device and a method thereof. The USB multi-functions device is capable of supporting a plurality of functions for a USB host, has a first software module installed to support a first selection of the functions, and comprises a function switch, a memory, and a controller. The function switch receives an input signal unrelated to any previous signal to switch from the first to a second selection of functions. The memory comprises a switch program executable by a controller, the first software module supporting the first selection of the functions and a second software module supporting the second selection of the functions. The controller executes the switch program to determine the second selection of the functions based on the input signal, and installs the second software module. | 04-18-2013 |
20130223129 | MEASURING ELECTRICAL RESISTANCE - In at least one embodiment, a method includes applying an input voltage external to a semiconductor chip to a first circuit of the semiconductor chip to generate an output voltage external to the semiconductor chip. The first circuit is electrically coupled to a resistive device. A logic state of the resistive device is determined based on a logic state of the external output voltage | 08-29-2013 |
Po-Hung Kuo, Taipei City TW
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20130057459 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, a plurality of pixel structures and a plurality of resistance compensating devices is provided. The substrate has a display region and a scanning signal input region beside the display region. The pixel structures are disposed in the display region. Each of the pixel structures includes a scan line, a data line, an active device and a pixel electrode. The data line is disposed in stagger with the scan line. The active device is electrically connected with the scan line and the data line. The pixel electrode is electrically connected with the active device. Each of the resistance compensating devices and a scan line of a corresponding pixel structure are connected in parallel. Resistances of the resistance compensating devices gradually decrease from a region close to the scanning signal input region to another region away the scanning signal input region. | 03-07-2013 |
Po-Hung Lai, Hsinchu TW
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20140362565 | LIGHT EMITTING DEVICE - This disclosure discloses a light-emitting device. The light-emitting device comprises: a first electrode part; a second electrode part; a third electrode part, spaced apart from the first electrode part and the second electrode part; and a light-emitting unit partially covering the first electrode part and the second electrode part and fully covering the second electrode part, the light-emitting unit having a conductive structure contacting the second electrode part. | 12-11-2014 |
Po-Hung Li, Hsinchu TW
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20150311818 | LOAD IMPEDANCE ESTIMATION AND REPETITIVE CONTROL METHOD CAPABLE OF ALLOWING INDUCTANCE VARIATION FOR INVERTER - The present invention provides a load impedance estimation and repetitive control method capable of allowing inductance variation for an inverter, wherein the method is applied for predicting corresponding next-period switching duty cycles for four switching member sets of the inverter by way of sampling three phase voltages and calculating next-period voltage compensations based on the previous line-period voltage compensations. Moreover, during the calculation and prediction, the method also involves the inductance variations of the output inductors of the inverter into the load impedance estimation matrix equation. Therefore, the three phases four wires inverter with the presented load impedance estimation and repetitive control method can provide a steady output voltage to the loads even if the originally-connected loads are replaced with other different loads. Thus, this load impedance estimation and repetitive control method can indeed improve the drawbacks of the inverter controller based on conventional DQ transformation method. | 10-29-2015 |
Po-Hung Lin, Zhubei TW
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20090113367 | ANALOG IC PLACEMENT USING SYMMETRY-ISLANDS - A placement tool searches for an optimal placement for a plurality of device modules within an integrated circuit (IC) including symmetry groups formed by device modules that are to be symmetrically placed. The tool employs a hierarchical B*-tree (HB*-tree) representation of a trial placement wherein each symmetry group and each module not included in a symmetry group is represented by a separate node of the HB*-tree. Each symmetry group node maps to a symmetry island placement for the symmetry group satisfying all symmetry and other placement constraints on the symmetry group. The placement tool employs a simulated annealing technique to iteratively perturb the HB*-tree representation to produce a sequence of trial placements, and uses a cost function to evaluate the quality of each trial placement. | 04-30-2009 |
Po-Hung Lin, Tainan City TW
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20140322376 | MOLDING MACHINE - A molding machine includes a machine table, a mold unit and a pair of positioning units. The mold unit includes first and second molds mounted on the machine table and movable between a mold-closing position and a mold-opening position. The first and second molds abut against each other in the mold-closing position. Each of the positioning units includes a first positioner connected to the first mold, and a second positioner connected to the second mold. When the first and second molds are in the mold-closing position, the first and second positioners are operable to move to a locked state, where the first positioner is held by the second positioner to restrain the first and second molds from deforming away from each other. | 10-30-2014 |
Po-Hung Lin, Jhubei TW
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20090235219 | HIERARCHICAL ANALOG IC PLACEMENT SUBJECT TO SYMMETRY, MATCHING AND PROXIMITY CONSTRAINTS - A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement. | 09-17-2009 |
Po-Hung Lin, Chiayi TW
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20150067626 | KNOWLEDGE-BASED ANALOG LAYOUT GENERATOR - A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design. | 03-05-2015 |
Po-Hung Shen, Miao-Li County TW
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20150264805 | DISPLAY DEVICE - The disclosure provides a display device including a first substrate, a display region disposed above the first substrate; a second substrate; a sealant disposed between the first substrate and the second substrate and outside the display region; and, a plurality of spacers disposed within the sealant. In particular, the first substrate and the second substrate are bonded together via the sealant. Further, the first substrate has a side wall including a first cutting crack surface and a first median crack surface, wherein a roughness of the first cutting crack surface is different from that of the first median crack surface. | 09-17-2015 |
Po-Hung Tsou, Xiamen CN
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20120043566 | AlGaInP Light-Emitting Diode Having Vertical Structure and Method for Manufacturing the Same - A method for manufacturing the AlGaInP LED having a vertical structure is provided, including: growing, epitaxially, a buffer layer, an n-type contact layer, an n-type textured layer, a confined layer, an active layer, a p-type confined layer and a p-type window layer in that order on a temporary substrate, to form a texturable epitaxial layer; forming a transparent conducting film with periodicity on the p-type window layer of the epitaxial layer, forming a regulated through-hole on the transparent conducting film, and filling the through-hole with a conducting material; forming a total-reflection metal layer on the transparent conducting film; bonding a permanent substrate with the texturable epitaxial layer via a bonding layer, and bring the total-reflection metal layer into contact with the bonding layer; removing the temporary substrate and the buffer layer; forming an n-type extension electrode on the exposed n-type contact layer; removing the n-type contact layer, and forming a pad on the n-type textured layer; and forming a p-type electrode on a back of the permanent substrate. The transparent multilayered film with periodicity provides a greater reflectivity difference and hence brings better results than the conventional reflector consisting of single-layered, or, non-periodic, transparent films; and light-emitting efficiency is enhanced. | 02-23-2012 |
Po-Hung Wang, Fongshan City TW
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20090168045 | THREE-DIMENSIONAL SURROUND SCANNING DEVICE AND METHOD THEREOF - A three-dimensional surround scanning device and a method thereof are described, which are adopted to perform surround scanning on a scene area, so as to construct a three-dimensional model. The device includes an image acquisition element, a first moving mechanism, a range acquisition element, and a controller. The controller controls the image acquisition element, the range acquisition element, and the first moving mechanism to perform three-dimensional image acquisition, so as to obtain a two-dimensional image covering the scene area, depth information with three-dimensional coordinates, and corresponding position signals. The controller rearranges and combines the two-dimensional image, position signals, and depth information, so as to construct the three-dimensional model. | 07-02-2009 |