Po-Han

Po-Han Chang, Nantou TW

Patent application number	Description	Published
20120311820	Knob and process of manufacturing same - A knob and process of manufacturing same is provided. The knob includes a knob portion formed of plastic; and a shank portion comprising a first hollow cylindrical member including an annular flange extending outward at one end, and a second hollow cylindrical member including an annular flange extending outward at one end, the annular flange of the first hollow cylindrical member being disposed in alignment with the annular flange of the second hollow cylindrical member. The whole second hollow cylindrical member and a portion of the first hollow cylindrical member of the shank portion are within the knob portion. The plastic knob portion has increased traction.	12-13-2012

Po-Han Chen, Chishang Township TW

Patent application number	Description	Published
20130064263	VERTICAL CAVITY SURFACE EMITTING LASER AND MANUFACTURING METHOD THEREOF - The present invention discloses a manufacturing method of vertical cavity surface emitting laser. The method includes following steps: providing a substrate; forming an epitaxial layer stack including an aluminum-rich layer; forming an ion-doping mask including a ring-shaped opening; doping ions in the epitaxial layer stack through the ring-shaped opening and forming a ring-shaped ion-doped region over the aluminum-rich layer; forming an etching mask on the ion-doping mask for covering the ring-shaped opening of the ion-doping mask; etching the epitaxial layer stack through the etching mask and ion-doping mask for forming an island platform; oxidizing the aluminum-rich layer for forming a ring-shaped oxidized region. In addition, the present invention also discloses a vertical cavity surface emitting laser manufactured by the above mentioned method.	03-14-2013

Po-Han Chen, Taipei Hsien TW

Patent application number	Description	Published
20120094707	Apparatuses, Systems, and Methods for Connection Establishment - A wireless communications device with a wireless module and a controller module is provided. The wireless module performs wireless transceiving to and from a service network. The controller module transmits a connection request message to the service network via the wireless module, and receives, on a downlink shared channel, a connection rejection message corresponding to the connection request message from the service network via the wireless module. Also, the controller module determines whether the connection rejection message indicates that congestion has occurred on the downlink shared channel, and retransmits the connection request message and waits to receive, on a forward access channel, a subsequent response message from the service network via the wireless module, in response to the connection rejection message indicating that congestion has occurred on the downlink shared channel.	04-19-2012

Po-Han Chen, Taipei City TW

Patent application number	Description	Published
20130155615	ELECTRONIC EQUIPMENT AND EXPANSION APPARATUS THEREOF - An expansion apparatus suitable for an electronic apparatus is provided. The expansion apparatus includes a base, a supporter and an airflow guiding structure. The base has a first fan disposed therein. The supporter is pivoted to the base along a rotating axis and has a cooling channel. The cooling channel has a first port and a second port opposite to the first port. When the electronic apparatus is assembled to the supporter, the second port of the cooling channel faces to the electronic apparatus. The airflow guiding structure is disposed between the supporter and the base movably. When the supporter is pivoted relative to the base to an expanded state, an active airflow generated by the first fan is guided by the airflow guiding structure to pass through the base and the electronic apparatus. An electronic equipment including the expansion apparatus is also provided.	06-20-2013

Po-Han Chen, Taoyuan County TW

Patent application number	Description	Published
20120255652	METHOD FOR IMPROVING SURFACE MECHANICAL PROPERTIES OF NON-AUSTENITIC STAINLESS STEELS - A method for improving surface mechanical properties of non-austenitic stainless steels comprises steps of: providing a non-austenitic stainless steel material; placing the non-austenitic stainless steel material in an environment containing at least one austenite-stabilizing element, and implanting the austenite-stabilizing elements into a surface of the non-austenitic stainless steel material to form a modified layer enriched with the austenite-stabilizing elements; and placing the non-austenitic stainless steel material in a carbon-bearing atmosphere to make the modified layer in contact with the carbon-bearing atmosphere, and maintaining the non-austenitic stainless steel material at a carburizing temperature below 600° C. to implant carbon into the modified layer to form a carburized layer. The carburized layer enhances the surface hardness of the non-austenitic stainless steel material and enables it to apply to decorative components or structural components demanding high abrasion resistance, high surface hardness, and high corrosion resistance.	10-11-2012

Po-Han Huang, New Taipei City TW

Patent application number	Description	Published
20150152252	Heat Shrinkable Material-Enclosed Porous Particle - A heat shrinkable material-enclosed porous particle including a porous body that has a plurality of pores and a heat shrinkable material that encloses the porous body is disclosed. A method for preparing heat shrinkable material-enclosed porous particles is also disclosed.	06-04-2015

Po-Han Huang, Hsinchu County TW

Patent application number	Description	Published
20120210103	SYSTEM AND METHOD FOR MULTI-CORE SYNCHRONOUS DEBUGGING OF A MULTI-CORE PLATFORM - A system and a corresponding method for multi-core synchronous debugging of a multi-core platform including a plurality of cores are provided. The method includes the following steps. Transmit a core debugging instruction to one of the cores selected by a system debugging instruction or store a group setting included in the system debugging instruction according to the type of the system debugging instruction. Control every core in a group to start executing program instructions simultaneously according to another system debugging instruction. The group is a subset of the cores and the group setting indicates which ones of the cores are included in the group. Use a handshaking mechanism to control all cores of the group to enter a debug mode simultaneously when a debug event happens in any core of the group.	08-16-2012

Po-Han Huang, Hsinchu TW

Patent application number	Description	Published
20130301038	SYSTEM AND METHOD FOR NONDESTRUCTIVE MEASURING REFRACTIVE INDEX AND THICKNESS OF LENS - The present invention discloses a system and method for nondestructively measuring the refractive index and the central thickness of a lens. The system comprises a radius measurement module arranged for measuring the curvature radius of the first surface of the lens; a focus measurement module arranged for measuring the best focus distance of the first surface of the lens; and a calculation module arranged for performing the first or the second calculation process according to the lensmaker's formula. Wherein, when the central thickness is given, the calculation module performs the first calculation process according to the curvature radius, the best focus distance and the central thickness to calculate the refractive index. On the contrary, when the refractive index is given, the calculation module performs the second calculation process according to the curvature radius, the best focus distance and the refractive index to calculate the central thickness.	11-14-2013

Po-Han Lee, Taipei City TW

Patent application number	Description	Published
20090289345	ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.	11-26-2009
20100201568	METHOD FOR IMPLEMENTING GPS SURVEYING FIELD WORK PLANNING USING 3D TOPOGRAPHIC INFORMAITON AND METHOD FOR ANALYZING 3D TOPOGRAPHIC INFORMATION - A method for implementing GPS surveying field work planning by using three dimensional topographic information is provided, comprising the steps of: obtaining three dimensional topographic information according to the location of a GPS receiver; obtaining maximum topographic elevation angle information from the GPS receiver to the terrain for each azimuth using the three dimension topographic information; obtaining elevation angle of satellites from the GPS receiver according to the satellite ephemeris or almanac; determining whether observation is usable according to the maximum topographic elevation angle information along the satellite bearings, and the elevation angle of satellites; and estimating the positioning accuracy according to the usable satellite observations.	08-12-2010
20110169139	CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.	07-14-2011
20110169159	CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.	07-14-2011
20130153933	CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a sensor region formed in the semiconductor substrate; a light emitting device disposed on the second surface of the semiconductor substrate; at least one first conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the sensor region; at least one second conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the light emitting device; and an insulating layer located on the semiconductor substrate to electrically insulate the semiconductor substrate from the at least one first conducting bump and the at least one second conducting bump.	06-20-2013
20150123231	SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.	05-07-2015
20150123285	CHIP DEVICE PACKAGES AND FABRICATION METHODS THEREOF - A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the second surface of the semiconductor substrate. A protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. A through hole is disposed on the first surface of the semiconductor substrate. A buffer material that is different from the material of the protection layer is disposed in the through hole and covered by the protection layer.	05-07-2015
20150132949	FABRICATION METHODS OF CHIP DEVICE PACKAGES - A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.	05-14-2015

Po-Han Wang, Taipei City TW

Patent application number	Description	Published
20100295852	GRAPHICS PROCESSING SYSTEM WITH POWER-GATING CONTROL FUNCTION, POWER-GATING CONTROL METHOD, AND COMPUTER PROGRAM PRODUCTS THEREOF - The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.	11-25-2010