| Patent application number | Description | Published |
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| 20080231499 | LOCATION TRACKING OF MOBILE PHONE USING GPS FUNCTION - A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO. | 09-25-2008 |
| 20090213522 | ON-CHIP ADJUSTMENT OF MIMCAP AND VNCAP CAPACITORS - One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors. | 08-27-2009 |
| 20120108210 | LOCATION TRACKING OF MOBILE PHONE USING GPS FUNCTION - A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO. | 05-03-2012 |
| 20120176259 | FLASH ANALOG TO DIGITAL CONVERTER WITH METHOD AND SYSTEM FOR DYNAMIC CALIBRATION - A flash analog to digital converter and a method and system for dynamically calibrating the flash analog to digital converter. The analog to digital converter may include a track and hold circuit and a plurality of comparators. The analog to digital converter may also include an under-sampling circuit configured to convert a digitized reference signal into an under-sampled digitized reference signal with a frequency of the calibration frequency divided by a positive number M. The under-sampling circuit may be further configured to calibrate a subsequent signal based on the under-sampled digitized reference signal. | 07-12-2012 |
| 20130063218 | FULLY DECOUPLED LC-TANK BASED OSCILLATOR TOPOLOGY FOR LOW PHASE NOISE AND HIGH OSCILLATION AMPLITUDE APPLICATIONS - There is provided a tank based oscillator. The oscillator includes one or more active devices, one or more passive devices, and a tank circuit decoupled from the active devices using at least one of the one or more passive devices. A coupling ratio between the tank circuit and the one or more active devices is set such that a maximum value of an oscillation amplitude of the tank circuit is limited based upon a breakdown of only the one or more passive devices. | 03-14-2013 |
| 20140042442 | RELIABLE PHYSICAL UNCLONABLE FUNCTION FOR DEVICE AUTHENTICATION - The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device. | 02-13-2014 |
| 20140184439 | SCALABLE POLARIMETRIC PHASED ARRAY TRANSCEIVER - A polarimetric transceiver front-end includes two receive paths configured to receive signals from an antenna, each receive path corresponding to a respective polarization. Each front-end includes a variable amplifier and a variable phase shifter; a first transmit path configured to send signals to the antenna, where the transmit path is connected to the variable phase shifter of one of the two receive paths and includes a variable amplifier; and a transmit/receive switch configured to select between the first transmit path and the two receive paths for signals, where the transmit/receive switch includes a quarter-wavelength transmission line that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state. | 07-03-2014 |
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| 20090108349 | HIGH-PERFORMANCE FET DEVICE LAYOUT - A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor. | 04-30-2009 |
| 20090132082 | STRIPED ON-CHIP INDUCTOR - Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters. | 05-21-2009 |
| 20090152612 | HIGH YIELD, HIGH DENSITY ON-CHIP CAPACITOR DESIGN - A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance. | 06-18-2009 |
| 20090278207 | Electromigration-Complaint High Performance FET Layout - An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor. | 11-12-2009 |
| 20100259107 | Systems and Methods for Providing Power to a Device Under Test - Systems and methods for providing power to a device under test are prcn ided. In some embodiments, systems for providing power to a device under test are provided, the systems comprising a power source for providing an alternating current, a probe having a probe inductor coupled to the power source; and a device under test having a device inductor magnetically coupled to the probe inductor, and having a circuit to be tested that receives power produced in the device inductor, In some embodiments, devices that receive power from a probe having an inductor that is coupled to an alternating current power source are provided, the devices comprising: a device inductor magnetically coupled to the probe inductor; and a circuit to be tested that receives power produced in the device inductor. | 10-14-2010 |
| 20100295156 | STRUCTURE FOR SYMMETRICAL CAPACITOR - Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance. | 11-25-2010 |
| 20100297825 | Passive Components in the Back End of Integrated Circuits - Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members. | 11-25-2010 |
| 20120112819 | ELECTROMIGRATION-COMPLAINT HIGH PERFORMANCE FET LAYOUT - An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor. | 05-10-2012 |
| 20120188109 | Track and Hold Amplifiers and Digital Calibration for Analog-to-Digital Converters - An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs. | 07-26-2012 |
| 20120223411 | STRIPED ON-CHIP INDUCTOR - Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters. | 09-06-2012 |
| 20130207274 | WAFER-SCALE PACKAGE STRUCTURES WITH INTEGRATED ANTENNAS - Wafer-scale packaging structures and methods are provided for integrally packaging antenna structures with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems for millimeter wave (mmWave) and Terahertz (THz) applications. For example, a chip package includes an RFIC chip, an antenna structure and an interface layer. The RFIC chip includes a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate. The antenna structure includes an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material. The interface layer connects the antenna structure to the BEOL structure of the RFIC chip. | 08-15-2013 |
| 20140071021 | HYBRID ON-CHIP AND PACKAGE ANTENNA - Antenna devices, antenna systems and methods of their fabrication are disclosed. One such antenna device includes a semiconductor chip and a chip package. The semiconductor chip includes at least one antenna that is integrated into a dielectric layer of the semiconductor chip and is configured to transmit electromagnetic waves. In addition, the chip package includes at least one ground plane, where the semiconductor chip is mounted on the chip package such that the ground plane(s) is disposed at a predetermined distance from the antenna to implement a reflection of at least a portion of the electromagnetic waves. | 03-13-2014 |
| 20140327468 | PHYSICAL UNCLONABLE FUNCTION GENERATION AND MANAGEMENT - Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include PUF elements arranged in series and in parallel with respect to each other to facilitate the measurement of the differentials and generation of a resulting bit sequence for purposes of authenticating the chip. Other embodiments are directed to determining and filtering reliable and unreliable states that can be employed to authenticate a chip. | 11-06-2014 |
| 20140327469 | PHYSICAL UNCLONABLE FUNCTION GENERATION AND MANAGEMENT - Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In accordance one such method, a test voltage is applied to a PUF system including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, where the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. In addition, the PUF system is measured to obtain at least one differential of states between the first subset of PUF elements and the second subset of PUF elements. Further, the method includes outputting an authentication sequence for the circuit that is based on the one or more differentials of states. | 11-06-2014 |
