Patent application number | Description | Published |
20080299718 | DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATION FOR PROTECTING LOW-K DIELECTRICS - A method of forming single or dual damascene interconnect structures using either a via-first or trench first approach includes the steps of providing a substrate surface having an etch-stop layer thereon, a low-k dielectric layer on the etch-stop layer, and a dielectric capping layer on the low-k dielectric layer. In the single damascene process using trench pattern, a trench is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the via-first process, using a via pattern, the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the trench first process, using the via pattern the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the single damascene or either via-first or trench-first dual damascene embodiment, the capping layer is retained over the low-k dielectric layer on top surfaces of the trench into the metal processing, generally including CMP processing, wherein the CMP process removes at least a portion, and in one embodiment the entire, capping layer. | 12-04-2008 |
20080305625 | POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS - A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth. | 12-11-2008 |
20090017563 | PLASMA TREATMENT AND REPAIR PROCESSES FOR REDUCING SIDEWALL DAMAGE IN LOW-K DIELECTRICS - A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the substrate including an etch-stop layer, a low-k dielectric layer, and a hardmask layer. The method further includes the steps of patterning a photoresist masking layer on the dielectric stack to define a plurality of feature defining regions and plasma processing the substrate in a plasma-based reactor, The processing step includes etching a plurality of features into the hardmask layer and at least a portion of the low-k dielectric layer and performing a plasma treatment process in situ in the plasma-based reactor, where the plasma treatment process includes flowing at least one hydrocarbon into the reactor and generating a plasma, where a mass flow rate of the hydrocarbon is at least 0.1 sccm. The method also includes forming a metal conductor in the plurality of features. | 01-15-2009 |
20090081864 | SiC Film for Semiconductor Processing - A silicon carbide (SiC) film for use in backend processing of integrated circuit manufacturing, is generated by including hydrogen in the reaction gas mixture. This SiC containing film is suitable for integration into etch stop layers, dielectric cap layers and hard mask layers in interconnects of integrated circuits. | 03-26-2009 |
20090111224 | FUSI INTEGRATION METHOD USING SOG AS A SACRIFICIAL PLANARIZATION LAYER - A method for making a transistor | 04-30-2009 |
20100041231 | FUSI Integration Method Using SOG as a Sacrificial Planarization Layer - A method for making a transistor | 02-18-2010 |
20110034023 | SILICON CARBIDE FILM FOR INTEGRATED CIRCUIT FABRICATION - A silicon carbide (SiC) film for use in backend processing of integrated circuit manufacturing, is generated by including hydrogen in the reaction gas mixture. This SiC containing film is suitable for integration into etch stop layers, dielectric cap layers and hardmask layers in interconnects of integrated circuits. | 02-10-2011 |
20110143533 | POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS - A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth. | 06-16-2011 |