Patent application number | Description | Published |
20080303168 | STRUCTURE FOR PREVENTING PAD PEELING - A structure for preventing pad peeling includes a semiconductor substrate, a dielectric layer, a pad, and a protective layer. The semiconductor substrate has an active circuit structure. The dielectric layer is disposed on the semiconductor substrate and has an opening located in the dielectric layer above an edge position of the corresponding active circuit structure. Besides, the opening exposes a part of the surface of the active circuit structure. The pad disposed above the semiconductor substrate covers the dielectric layer above the position of the corresponding active circuit structure and fills up the opening. The protective layer is disposed on the dielectric layer and covers the edge of the pad. | 12-11-2008 |
20080303177 | BONDING PAD STRUCTURE - A bonding pad structure including a bonding pad and a passivation layer is described. The bonding pad is disposed on a chip. The passivation layer covers the bonding pad. In addition, the passivation layer has a first opening exposing a bonding region of the bonding pad and a second opening exposing a probing region of the bonding pad, respectively. | 12-11-2008 |
20090001522 | DIE SEAL RING AND WAFER HAVING THE SAME - A die seal ring disposed in a die and surrounding an integrated circuit region of the die is described. The die seal ring has at least two different local widths. | 01-01-2009 |
20090008782 | INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF - An integrated circuit structure is provided. The integrated circuit structure includes a dielectric layer, a conductive structure, a low-k dielectric layer and a plug. The conductive structure is disposed in the dielectric layer, having a recess portion. The low-k dielectric layer is disposed on the dielectric layer. The plug is disposed in the low-k dielectric layer and has a protruding bonding portion on the bottom of the plug. The bonding portion is extended into the dielectric layer and connected to the recess portion of the conductive structure. | 01-08-2009 |
20090014717 | TEST IC STRUCTURE - A test IC structure is described, which is disposed in a scribe line region of a wafer and includes first and second test keys, first and second conductive plugs, first and second test pads, and a passivation layer over the scribe line region. The first/second test key includes a first/second active device and a first/second interconnect structure electrically connected thereto, wherein the second test key is arranged substantially parallel with the first one. The first/second plug is disposed over the first/second interconnect structure and contacts with the upmost metal layer thereof. The first/second test pad is disposed over the first and the second test keys and contacts with the first/second conductive plug. The passivation layer has therein a first opening exposing a portion of the first test pad and a second opening exposing a portion of the second test pad. | 01-15-2009 |
20090014870 | SEMICONDUCTOR CHIP AND PACKAGE PROCESS FOR THE SAME - A semiconductor chip is provided. The semiconductor chip includes a chip and chip bump pads thereon. The chip bump pads include at least two chip bump pads that are physically connected. | 01-15-2009 |
20090283916 | CHIP STRUCTURE AND METHOD OF REWORKING CHIP - A method of reworking a chip includes providing a first chip and a second chip. The first and second chips have at least one first module and at least one second module, respectively. The first and second modules electrically connect with each other. The first module of the first chip has a defect. The second module of the second chip has a defect. The first module having a defect of the first chip is opened with the second module of the first chip, and the second module having a defect of the second chip is opened with the first module of the second chip. The first and second chips are stacked, and the second module of the first chip is electrically connects with the first module of the second chip. | 11-19-2009 |
20090294994 | BOND PAD STRUCTURE - A bond pad structure located over an active circuit structure is disclosed. The bond pad structure includes a bond pad, a passivation layer and a topmost metal layer in the active circuit structure. The passivation layer covers the bond pad and has an opening, and the opening exposes a part of the bond pad. The part of the topmost metal layer located under the opening serves as a supporting layer. The supporting layer has at least a slot, and the topmost metal layer is electrically connected to the bond pad through a plurality of via plugs. | 12-03-2009 |
20110278701 | Scribe line structure for wafer dicing - The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer. | 11-17-2011 |
20130009656 | TEST PAD STRUCTURE ON WAFER - A test pad structure on a wafer includes at least a scribe line positioned on a wafer, a pad region defined in the scribe line, and a metal pad positioned in the pad region. An area of the metal pad and an area of the pad region include a ratio, and the ratio is lower than equal to 50%. | 01-10-2013 |
20140054750 | Scribe line structure for wafer dicing and method of making the same - A scribe line structure between die regions is disclosed. The scribe line structure includes a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in the dielectric layer on the substrate, the plurality of metal structures comprising metal layers and metal vias, wherein the metal vias are disposed on the dicing path and regions outside the dicing path and the metal vias on the dicing path have a lower metal density than the metal vias not on the dicing path. | 02-27-2014 |