Patent application number | Description | Published |
20110056938 | VENT VALVE - In one embodiment, the valve comprises: (a) a housing configured to interengage with a container, and having at least one axis and at least one aperture; (b) a first poppet axially movably within said housing between a first closed position and a first open position; (c) a second poppet axially movable within said first poppet between a second closed position and a second open position; (d) a first seal between said first poppet and said housing; (e) a second seal between said first poppet and said second poppet; (f) a first resilient member disposed within a first space between said housing and said first poppet, and having a resilient force sufficient to hold said first poppet in said first closed position such that said first poppet urges said first seal against said housing when a pressure differential axially across said first poppet is below a first point, and to allow said first poppet to move in said first direction to said first open position when said fluid pressure differential exceeds said first point; and (g) a second resilient member disposed within a second space between said first poppet and said second poppet, and having a resilient force sufficient to hold said second poppet in said closed position such that that said second poppet urges said second seal against said first poppet when a pressure differential axially across said second poppet is below a second point, and to allow said second poppet to move in a second direction, different from said first direction, to said second open position when said pressure differential exceeds said second point. | 03-10-2011 |
20120313030 | SPRING-CAPTURE ASSEMBLY FOR A SPRING-BIASED MECHANISM AND PRESSURE RELIEF VALVE INCLUDING SAME - A spring capture assembly is provided for securing a compression spring of a spring-biased mechanism, such as a spring-biased pressure relief valve, to permit disassembly of the mechanism without risk of damage or injury associate with rapid resiling of the spring from a compressed state. The assembly includes a tool, a housing having an opening for admitting passage of the tool and capturing the spring at one end, a spring retainer, and a compression spring mounted within the housing and captured at one end by said housing and toward an opposite end by the spring retainer. The tool is adapted for mating with the spring retainer and the housing to compress the spring therebetween. The spring capture assembly may be incorporated into a pressure relief valve for venting pressure and/or vacuum from a pressure vessel. Provided also is a method for disassembling a spring-biased mechanism including a spring capture assembly. | 12-13-2012 |
Patent application number | Description | Published |
20100319962 | SELF-ALIGNED NANO-SCALE DEVICE WITH PARALLEL PLATE ELECTRODES - A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates. | 12-23-2010 |
20110092069 | SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES - A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material. | 04-21-2011 |
20110101537 | HYBRID BONDING INTERFACE FOR 3-DIMENSIONAL CHIP INTEGRATION - Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions. | 05-05-2011 |
20120160295 | SOLAR CELL CLASSIFICATION METHOD - A method for characterizing the electronic properties of a solar cell to be used in a photovoltaic module comprises the steps of performing a room temperature IV curve measurement of the solar cell and classifying the solar cell based on this IV curve measurement. In order to take stress-related effects into account, the solar cells are reclassified depending on the result of an additional measurement conducted on the solar cells under stress. This stress-related measurement may be gained from light induced thermography (LIT) yielding information on diode shunt areas within the solar cell. | 06-28-2012 |
20120194792 | METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY - A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error. | 08-02-2012 |
Patent application number | Description | Published |
20090017616 | METHOD FOR FORMING CONDUCTIVE STRUCTURES - A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer. | 01-15-2009 |
20090085210 | STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer. | 04-02-2009 |
20090108381 | Low temperature bi-CMOS compatible process for MEMS RF resonators and filters - A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material. The method of removal of the sacrificial material is by an oxygen plasma or an anneal in an oxygen containing ambient. A method of vacuum encapsulation of the MEMS resonator or filter is provided through means of a cavity containing the MEMS device, filled with additional sacrificial material, and sealed. Access vias are created through the membrane sealing the cavity; the sacrificial material is removed as stated previously, and the vias are re-sealed in a vacuum coating process. | 04-30-2009 |
20100038777 | METHOD OF MAKING A SIDEWALL-PROTECTED METALLIC PILLAR ON A SEMICONDUCTOR SUBSTRATE - A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon. | 02-18-2010 |
20110109405 | Low Temperature BI-CMOS Compatible Process For MEMS RF Resonators and Filters - A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane. | 05-12-2011 |
20120270351 | LOW TEMPERATURE BI-CMOS COMPATIBLE PROCESS FOR MEMS RF RESONATORS AND FILTERS - A method of removal of a first and second sacrificial layer wherein an O | 10-25-2012 |