Patent application number | Description | Published |
20090004799 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FORMATION OF AT LEAST ONE SIDEWALL SPACER STRUCTURE - According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is formed over the first feature. At least one etch process adapted to form a sidewall spacer structure adjacent the second feature from a portion of the material layer is performed. The mask protects a portion of the material layer over the first feature from being affected by the at least one etch process. An ion implantation process is performed. The mask remains over the first feature during the ion implantation process. | 01-01-2009 |
20090142900 | METHOD FOR CREATING TENSILE STRAIN BY SELECTIVELY APPLYING STRESS MEMORIZATION TECHNIQUES TO NMOS TRANSISTORS - By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps. | 06-04-2009 |
20090273036 | METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING PROCESSES BY MODIFYING A PARASITIC PN JUNCTION - By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced. | 11-05-2009 |
20110024846 | LEAKAGE CONTROL IN FIELD EFFECT TRANSISTORS BASED ON AN IMPLANTATION SPECIES INTRODUCED LOCALLY AT THE STI EDGE - In a static memory cell, the failure rate upon forming contact elements connecting an active region with a gate electrode structure formed above an isolation region may be significantly reduced by incorporating an implantation species at a tip portion of the active region through a sidewall of the isolation trench prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region. | 02-03-2011 |
20110101469 | STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CORNER ROUNDING AT THE TOP OF THE GATE ELECTRODE - In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage. | 05-05-2011 |
20110156172 | ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A RECESS PRIOR TO THE WELL IMPLANTATION - When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack. | 06-30-2011 |
20110291163 | Reduction of Defect Rates in PFET Transistors Comprising a Si/Ge Semiconductor Material Formed by Epitaxial Growth - In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors. | 12-01-2011 |
20120001254 | Transistor With Embedded Si/Ge Material Having Reduced Offset and Superior Uniformity - In sophisticated semiconductor devices, a strain-inducing embedded semiconductor alloy may be provided on the basis of a crystallographically anisotropic etch process and a self-limiting deposition process, wherein transistors which may not require an embedded strain-inducing semiconductor alloy may remain non-masked, thereby providing superior uniformity with respect to overall transistor configuration. Consequently, superior strain conditions may be achieved in one type of transistor, while generally reduced variations in transistor characteristics may be obtained for any type of transistors. | 01-05-2012 |
20120025318 | Reduced Topography in Isolation Regions of a Semiconductor Device by Applying a Deposition/Etch Sequence Prior to Forming the Interlayer Dielectric - Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled. | 02-02-2012 |
20120153401 | Differential Threshold Voltage Adjustment in PMOS Transistors by Differential Formation of a Channel Semiconductor Material - In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors. | 06-21-2012 |
20120161250 | Transistor Comprising High-K Metal Gate Electrode Structures Including a Polycrystalline Semiconductor Material and Embedded Strain-Inducing Semiconductor Alloys - When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for. | 06-28-2012 |
20120202326 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure. | 08-09-2012 |
20120235249 | REDUCING DEFECT RATE DURING DEPOSITION OF A CHANNEL SEMICONDUCTOR ALLOY INTO AN IN SITU RECESSED ACTIVE REGION - When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled. | 09-20-2012 |
20120241816 | Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material - When forming sophisticated P-channel transistors, the metal silicide agglomeration in a germanium-containing strain-inducing semiconductor alloy may be avoided or at least significantly reduced by incorporating a carbon and/or nitrogen species in a highly controllable manner. In some illustrative embodiments, the carbon species or nitrogen species is incorporated during the epitaxial growth process so as to form a surface layer of the strain-inducing semiconductor alloy with a desired nitrogen and/or carbon concentration and with a desired thickness without unduly affecting any other device areas. | 09-27-2012 |
20120241864 | Shallow Source and Drain Architecture in an Active Region of a Semiconductor Device Having a Pronounced Surface Topography by Tilted Implantation - In sophisticated semiconductor devices, a shallow drain and source concentration profile may be obtained for active regions having a pronounced surface topography by performing tilted implantation steps upon incorporating the drain and source dopant species. In this manner, a metal silicide may be reliably embedded in the drain and source regions. | 09-27-2012 |
20120280289 | Method of Increasing the Germanium Concentration in a Silicon-Germanium Layer and Semiconductor Device Comprising Same - Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium. | 11-08-2012 |
20120282744 | Reduced Threshold Voltage-Width Dependency and Reduced Surface Topography in Transistors Comprising High-K Metal Gate Electrode Structures by a Late Carbon Incorporation - Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. On the other hand, increased yield losses observed in conventional strategies may be reduced by taking into consideration the increased etch rate of the carbon-doped silicon material in the active regions. To this end, the carbon species may be incorporated after the application of at least some aggressive wet chemical processes. | 11-08-2012 |
20120302023 | PMOS Threshold Voltage Control by Germanium Implantation - Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a P-active region in a silicon containing semiconducting substrate, performing an ion implantation process to implant germanium into the P-active region to form an implanted silicon-germanium region in the P-active region, and forming a gate electrode structure for a PMOS transistor above the implanted silicon-germanium region. | 11-29-2012 |
20120305995 | PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL ON THE BASIS OF A SEED LAYER - In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process. | 12-06-2012 |
20120309182 | Method of Forming Sidewall Spacers Having Different Widths Using a Non-Conformal Deposition Process - Disclosed herein is a method of forming sidewall spacers for a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate. performing a non-conformal deposition process to deposit a layer of spacer material above the gate electrode structure and performing an anisotropic etching process on the layer of spacer material to define a first sidewall spacer proximate a first side of the gate electrode structure and a second sidewall spacer proximate a second side of the gate electrode structure, wherein the first and second sidewall spacers have different widths. | 12-06-2012 |
20130026582 | PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION - Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions. | 01-31-2013 |
20130032864 | TRANSISTOR WITH BOOT SHAPED SOURCE/DRAIN REGIONS - Devices are formed with boot shaped source/drain regions formed by isotropic etching followed by anisotropic etching. Embodiments include forming a gate on a substrate, forming a first spacer on each side of the gate, forming a source/drain region in the substrate on each side of the gate, wherein each source/drain region extends under a first spacer, but is separated therefrom by a portion of the substrate, and has a substantially horizontal bottom surface. Embodiments also include forming each source/drain region by forming a cavity to a first depth adjacent the first spacer and forming a second cavity to a second depth below the first cavity and extending laterally underneath the first spacers. | 02-07-2013 |
20130032901 | FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH - Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA. | 02-07-2013 |
20130052819 | Methods of Forming Metal Silicide Regions on Semiconductor Devices Using Different Temperatures - Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature. | 02-28-2013 |
20130065329 | Superior Integrity of High-K Metal Gate Stacks by Preserving a Resist Material Above End Caps of Gate Electrode Structures - When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance. | 03-14-2013 |
20130105900 | Methods of Forming PFET Devices With Different Structures and Performance Characteristics | 05-02-2013 |
20130105917 | Methods of Epitaxially Forming Materials on Transistor Devices | 05-02-2013 |
20130178045 | Method of Forming Transistor with Increased Gate Width - Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess. | 07-11-2013 |
20130214381 | METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench. | 08-22-2013 |
20130214392 | METHODS OF FORMING STEPPED ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES USING A SPACER TECHNIQUE - Disclosed herein are various methods of forming stepped isolation structures for semiconductor devices using a spacer technique. In one example, the method includes forming a first trench in a semiconducting substrate, wherein the first trench has a bottom surface, a width and a depth, the depth of the first trench being less than a target final depth for a stepped trench isolation structure, performing an etching process through the first trench on an exposed portion of the bottom surface of the first trench to form a second trench in the substrate, wherein the second trench has a width and a depth, and wherein the width of the second trench is less than the width of the first trench, and forming the stepped isolation structure in the first and second trenches. | 08-22-2013 |
20130221478 | METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY EMPLOYING A SPIN-ON GLASS MATERIAL OR A FLOWABLE OXIDE MATERIAL - Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices using a spin-on glass material or a flowable oxide material. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure comprised of an insulating material in at least the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench. | 08-29-2013 |
20130267044 | SUPERIOR INTEGRITY OF HIGH-K METAL GATE STACKS BY PRESERVING A RESIST MATERIAL ABOVE END CAPS OF GATE ELECTRODE STRUCTURES - When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance. | 10-10-2013 |
20130320415 | FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH - Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA. | 12-05-2013 |
20130344673 | SEMICONDUCTOR DEVICE FABRICATION METHODS - A method for fabricating a semiconductor device includes forming first and second gate structures overlying the semiconductor substrate, and depositing a layer of a silicide-resistant material over the first and second gate structures and over the semiconductor substrate. The method further includes forming sidewall spacers from the layer of silicide-resistant material adjacent the first gate structure and removing the silicide-resistant material adjacent the sidewall spacers to expose the silicon substrate in a source and drain region. Still further, the method includes implanting conductivity determining impurities in the source and drain region, depositing a silicide forming metal, and annealing the semiconductor device to form a silicide in the source and drain region. The silicide-resistant material is not removed from over the second gate structure so as to prevent silicide formation at the second gate structure. | 12-26-2013 |
20140131805 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET AND SUPERIOR UNIFORMITY - A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material. | 05-15-2014 |
20140167110 | PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION - Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions. | 06-19-2014 |
20140167119 | METHODS OF FORMING A SIDEWALL SPACER HAVING A GENERALLY TRIANGULAR SHAPE AND A SEMICONDUCTOR DEVICE HAVING SUCH A SPACER - A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure. | 06-19-2014 |
20140191332 | PFET DEVICES WITH DIFFERENT STRUCTURES AND PERFORMANCE CHARACTERISTICS - Disclosed herein is a device that includes a first PFET transistor formed in and above a first active region of a semiconducting substrate, a second PFET transistor formed in and above a second active region of the semiconducting substrate, wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different. | 07-10-2014 |
20140231907 | METHODS OF INDUCING A DESIRED STRESS IN THE CHANNEL REGION OF A TRANSISTOR BY PERFORMING ION IMPLANTATION/ANNEAL PROCESSES ON THE GATE ELECTRODE - One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e | 08-21-2014 |
20140252429 | CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH - Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure. | 09-11-2014 |
20140252557 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE STRUCTURES - Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion. | 09-11-2014 |
20140256135 | METHODS OF REMOVING GATE CAP LAYERS IN CMOS APPLICATIONS - One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor. | 09-11-2014 |
20140256137 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING AN IMPLANTATION OF IONS INTO A LAYER OF SPACER MATERIAL - A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material. | 09-11-2014 |
20140264617 | HK/MG PROCESS FLOWS FOR P-TYPE SEMICONDUCTOR DEVICES - The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel. | 09-18-2014 |
20140264632 | SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR HAVING A LAYER OF A STRESS-CREATING MATERIAL AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure is provided including a transistor, the transistor including one or more elongated semiconductor regions, each of the one or more elongated semiconductor regions having a channel region, a gate electrode, wherein the gate electrode is provided at least at two opposite sides of each of the one or more elongated semiconductor regions, and a layer of a stress-creating material, the stress-creating material providing a variable stress, wherein the layer of stress-creating material is arranged to provide a stress at least in the channel region of each of the one or more elongated semiconductor regions, the stress provided in the channel region of each of the one or more elongated semiconductor regions being variable. | 09-18-2014 |
20140273367 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH GATE ELECTRODE STRUCTURE PROTECTION - Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure. | 09-18-2014 |
20140273375 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SEMICONDUCTOR SUBSTRATE PROTECTION - Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate. | 09-18-2014 |
20150021693 | ENHANCING TRANSISTOR PERFORMANCE AND RELIABILITY BY INCORPORATING DEUTERIUM INTO A STRAINED CAPPING LAYER - When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform—in combination with further subsequently performed process steps—a sufficient diffusion of deuterium to the gate dielectrics. | 01-22-2015 |