Patent application number | Description | Published |
20100174851 | MEMORY SYSTEM CONTROLLER - The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes. | 07-08-2010 |
20100191874 | HOST CONTROLLER - The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device. | 07-29-2010 |
20100312973 | METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device. | 12-09-2010 |
20100313065 | OBJECT ORIENTED MEMORY IN SOLID STATE DEVICES - The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks. | 12-09-2010 |
20110032823 | PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL - The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication. | 02-10-2011 |
20110047366 | BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION - The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host. | 02-24-2011 |
20110051513 | METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES - The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell. | 03-03-2011 |
20110055436 | DEVICE TO DEVICE FLOW CONTROL - The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to device flow control includes a host and a chain of devices, including one or more memory device, coupled to each other and configured to communicate with the host device through a same host port. In one or more embodiments, at least one device in the chain is configured to regulate the flow of data by sending a token in downstream data packets, the token allowing devices downstream from the respective at least one device to send an upstream data packet to the respective at least one device. | 03-03-2011 |
20110078336 | STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION - The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host. | 03-31-2011 |
20110280084 | DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data. | 11-17-2011 |
20120069658 | METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES - The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell. | 03-22-2012 |
20120109896 | DATA SIGNAL MIRRORING - Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored. | 05-03-2012 |
20120110244 | COPYBACK OPERATIONS - Methods and systems for copyback operations are described. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the memory device, and programming the data to a second memory unit of the memory device. | 05-03-2012 |
20120182810 | METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES - The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells. | 07-19-2012 |
20120210025 | DEVICE TO DEVICE FLOW CONTROL - The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to device flow control includes a host and a chain of devices, including one or more memory device, coupled to each other and configured to communicate with the host device through a same host port. In one or more embodiments, at least one device in the chain is configured to regulate the flow of data by sending a token in downstream data packets, the token allowing devices downstream from the respective at least one device to send an upstream data packet to the respective at least one device. | 08-16-2012 |
20120243362 | ADVANCED DETECTION OF MEMORY DEVICE REMOVAL, AND METHODS, DEVICES AND CONNECTORS - Memory devices, connectors and methods for terminating an operation are provided, including a memory device configured to terminate an internal operation such as a programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may be configured to generate the removal signal, such as by including a dedicated removal terminal. The memory card may respond to the signal by terminating a programming or erase operation before power is lost. The removal terminal may have a dimension that is different from a dimension of a power terminal. Alternatively, the connector may be configured to generate a signal that causes a host to terminate programming or erase operations prior to memory card removal, such as by including a switch that is actuated when the memory device moves to a pre-power loss position. | 09-27-2012 |
20120281537 | PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL - The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication. | 11-08-2012 |
20120284466 | METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device. | 11-08-2012 |
20120290826 | BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION - The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host. | 11-15-2012 |
20130010537 | DEVICES AND METHODS OF PROGRAMMING MEMORY CELLS - Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, and further programming cells corresponding to the first page of data that will not likely be affected by coupling from programming the second page of data. | 01-10-2013 |
20130013816 | STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION - The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host. | 01-10-2013 |
20130013822 | HOST CONTROLLER - The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device. | 01-10-2013 |
20130051142 | MEMORY WITH THREE TRANSISTOR MEMORY CELL DEVICE - Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either the three transistor memory cell device or the non-volatile memory device. | 02-28-2013 |
20130051143 | MEMORY CELL COUPLING COMPENSATION - Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing. | 02-28-2013 |
20130058168 | METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES - The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell. | 03-07-2013 |
20130141985 | METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES - The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells. | 06-06-2013 |
20130219113 | MEMORY SYSTEM CONTROLLER - The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes. | 08-22-2013 |
20130268719 | REMAPPING AND COMPACTING IN A MEMORY DEVICE - Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device. | 10-10-2013 |
20130286736 | DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data. | 10-31-2013 |
20140016411 | DEVICES AND METHODS OF PROGRAMMING MEMORY CELLS - Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, and further programming cells corresponding to the first page of data that will not likely be affected by coupling from programming the second page of data. | 01-16-2014 |
20140025943 | BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION - The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host. | 01-23-2014 |
20140059251 | STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION - The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host. | 02-27-2014 |
20140098614 | METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES - The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell. | 04-10-2014 |
20140104951 | SENSING DATA STORED IN MEMORY - The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and configured to sense a page of memory cells coupled to an activated access line by pre-charging only a single subset of a number of data lines coupled to the page, wherein more than two subsets of data lines are coupled to the page and the single subset is coupled to those memory cells storing at least a portion of a single sector of data of the page, and sensing the single subset of the number of data lines to determine the at least a portion of the single sector of data. | 04-17-2014 |
20140108678 | HOST CONTROLLER - The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device. | 04-17-2014 |
20140126290 | MEMORY ARRAYS WITH A MEMORY CELL ADJACENT TO A SMALLER SIZE OF A PILLAR HAVING A GREATER CHANNEL LENGTH THAN A MEMORY CELL ADJACENT TO A LARGER SIZE OF THE PILLAR AND METHODS - The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size. | 05-08-2014 |
20140185620 | PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL - The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication. | 07-03-2014 |
20140233314 | MEMORY CELL COUPLING COMPENSATION - Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing. | 08-21-2014 |
20140254267 | MEMORY DEVICES WITH DIFFERENT SIZED BLOCKS OF MEMORY CELLS AND METHODS - In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a block is coupled to a respective select transistor, and wherein each of the select transistors coupled to the plurality of strings of the block is coupled to a common first select line. The plurality of blocks includes N block sizes, where N may be an integer greater than or equal to three. N−1 blocks of one block size of the N block sizes collectively include a first number of second select lines. A group of blocks consisting of a respective block of each remaining block size of the N block sizes collectively include a second number of second select lines that is equal to the first number of select lines or that is less than the first number of second select lines. | 09-11-2014 |
20140281811 | OBJECT ORIENTED MEMORY IN SOLID STATE DEVICES - The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks. | 09-18-2014 |
20140347932 | MEMORY WITH THREE TRANSISTOR MEMORY CELL DEVICE - Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either the three transistor memory cell device or the non-volatile memory device. | 11-27-2014 |
20140355355 | METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES - The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells. | 12-04-2014 |
20150078099 | SENSING DATA STORED IN MEMORY - The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and configured to sense a page of memory cells coupled to an activated access line by pre-charging only a single subset of a number of data lines coupled to the page, wherein more than two subsets of data lines are coupled to the page and the single subset is coupled to those memory cells storing at least a portion of a single sector of data of the page, and sensing the single subset of the number of data lines to determine the at least a portion of the single sector of data. | 03-19-2015 |