Peng, Hsinchu
Cheng-Chung Peng, Hsinchu TW
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20080266236 | Driving method of liquid crystal display device having dynamic backlight control unit - A dynamic control method for controlling backlight module of liquid crystal display (LCD) comprises steps of: receiving a frame data which is transferred to the LCD and consists a plurality of raw grayscale level; processing a statistical analysis for distribution of the plurality of raw grayscale level; and transferring a plurality of corrected grayscale level which is resulted from the statistical analysis corresponding to the raw grayscale level to the backlight control unit and a data modification simultaneously, wherein the backlight control unit uses the plurality of corrected grayscale level to modify brightness of backlight module and the data modification uses the plurality of corrected grayscale level to compare with the plurality of raw grayscale level for accurate display performance, so that the electrical power consumption is reduced and image quality is enhanced. | 10-30-2008 |
20110164206 | LIQUID CRYSTAL DISPLAY DEVICE - The present invention provides an improved type of liquid crystal (LC) display device with wide-viewing angle and high optical transmittance. The LC display of the present invention consists of: at least one LC alignment apparatus, which makes the LC molecules within the display area forming a continuous-domain or multi-domain alignments, and hence improve its wide-viewing-angle characteristics; a LC layer formed by Nematic type LC with chiral dopants, and with optimal parameters of the optical path difference Δnd and LC rotations of d/p ratio, such that LC molecules can be aligned along all radial directions to achieve optimal transmittance, and thus producing an wide-viewing-angle LC display improved transmittance without the formation of dark fringes in the display area. | 07-07-2011 |
20110199550 | LIQUID CRYSTAL DISPLAY DEVICE - A new type of liquid crystal display (LCD) device with improved high transmittance and wide-view-angle characteristics while without gray-level inversion at an inclined viewing angle is provided. The LCD device includes a first substrate with common electrodes, a second substrate with at least one pixel unit, a liquid crystal (LC) layer disposed between the first substrate and the second substrate, a first polarizer, and a second polarizer. The pixel unit has a pixel electrode, which is formed by at least one dense electrode area and at least one sparse electrode area. The LC molecules of the LC layer form a continuous-domain alignment after being driven by a voltage. | 08-18-2011 |
20140160412 | LATERAL ELECTRIC FIELD TYPE LIQUID CRYSTAL DISPLAY DEVICE HAVING NON-UNIFORM SPACINGS BETWEEN TWO ELECTRODES - A lateral electric field type liquid crystal display (LCD) device comprises a first substrate formed with a plurality of first electrodes and at least one second electrode, a second substrate and a liquid crystal layer disposed between the two substrates. Each first electrode comprises an array of electrode segments and every adjacent first and second electrodes have a minimum spacing smaller than a maximum spacing in between. Each second electrode is a strip electrode or also comprises an array of electrode segments. Each electrode segment is a V-shape electrode rotated with an angle or an electrode segment having at least an extruded portion and at least an intruded portion. The array of electrode segments may be a sinusoidal electrode. The first and second electrodes are oriented in parallel with or at a specific angle with respect to the data line of the lateral electric field type LCD device. | 06-12-2014 |
20140160415 | LIQUID CRYSTAL DISPLAY DEVICE HAVING ELECTRODES WITH ELONGATED APERTURES - A liquid crystal display (LCD) device comprises a first substrate formed with a first electrode, a second substrate formed with a second electrode and a liquid crystal layer disposed between the two substrates. The LCD device includes at least one pixel area having at least one display unit. In the display unit, the first or second electrode is formed with a plurality of elongated apertures arranged in parallel and positioned outwardly one by one from the center of the display unit along at least four different directions. The plurality of elongated apertures forms solid or dotted edges around the circumference of the first or second electrode. The solid or dotted edges of the first electrode may be aligned with or extend outwardly more or less than the solid or dotted edges of the second electrode from the center of the display unit. | 06-12-2014 |
Cheng-Tzu Peng, Hsinchu TW
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20120104916 | HARD DRIVE CARRYING DEVICE AND HARD DRIVE BOX THEREOF - A hard drive carrying device and its hard drive box can fasten a plurality of hard drive boxes in a containing slot of the supporting stand by utilizing simplified mechanism so that a user can rapidly open the locking of the hard drive box by pressing a pressing member to quickly take the hard drive box out from the supporting stand. A hard drive carrying device comprises a supporting stand with a plurality of containing slots, a plurality of hard drive boxes, wherein each hard drive box comprises a main frame, an engaging member and a lock protection member, wherein the lock protection member further comprises a sliding piece, a fastening elastic piece, a pressing member and an elastic member. The device uses the structural design to exactly thin the opening mechanism for the hard drive box to effectively reduce the occupied space so as to increase the actual application. | 05-03-2012 |
Chia-Ching Peng, Hsinchu TW
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20100211837 | Semiconductor test system with self-inspection of memory repair analysis - A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein. | 08-19-2010 |
Chien-Chung Peng, Hsinchu TW
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20130099254 | LIGHT EMITTING DIODE WITH CHAMFERED TOP PERIPHERAL EDGE - A light emitting diode includes a substrate and a light emitting structure. The light emitting structure includes a light outputting surface away from the substrate and a plurality of sidewalls adjoining the light outputting surface. A top peripheral edge interconnecting the light outputting surface and the sidewalls of the light emitting structure is a rounded top peripheral edge or a beveled top peripheral edge. A top surface of the substrate surrounding the light emitting structure is exposed to air and formed with micro-structures. | 04-25-2013 |
Chien Ming Peng, Hsinchu TW
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20140062832 | ANTENNA SUPPORT, ANTENNA DEVICE AND ANTENNA SUPPORT ASSEMBLY INCLUDING THE SAME - An antenna support, an antenna device and an antenna support assembly including the same are provided. The antenna support includes a tube-shaped support and at least one antenna fixing unit. The antenna fixing unit is disposed on the outer wall of the tube-shaped support for fixing an antenna unit. The antenna device includes the antenna unit and the antenna support. The antenna support assembly includes a plurality of antenna supports connected to each other at their ends. | 03-06-2014 |
20140085826 | ELECTRONIC DEVICE AND PLUG AND PLAY UNIT THEREOF - A plug and play unit is provided. The plug and play unit includes a unit housing, a joint, a substrate and a heat conductive member. The joint is connected to the unit housing. The substrate is disposed in the unit housing and the joint, wherein the substrate includes a heat conductive layer and a USB connection port. The heat conductive member thermally connects the joint to the heat conductive layer to transmit heat from the heat conductive layer to the joint. | 03-27-2014 |
20150043178 | ELECTRONIC EQUIPMENT AND PLUG-AND-PLAY DEVICE THEREOF - A plug-and-play device is provided. The plug-and-play device includes a device housing, a circuit board, a joint and an electromagnetic shielding frame. The circuit board is disposed in the device housing, including a substrate and a plurality of transmission pins, wherein the transmission pins are formed on the substrate. The transmission pins are connected to the joint. The electromagnetic shielding frame covers the transmission pins. | 02-12-2015 |
20150364811 | Wireless Transceiver - A wireless transceiver includes at least one antenna, a substrate, and a mechanical part on which the at least one antenna is disposed, wherein a relative position between the at least one antenna and the substrate is changed when an external force is applied to the mechanical part. | 12-17-2015 |
Chih-Chun Peng, Hsinchu TW
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20130341409 | Multi-Function Radio-Frequency Device, Computer System and Method of Operating Multi-Function Radio-Frequency Device - A multi-function Radio-Frequency device integrated into a computer system is disclosed and includes a substrate including a first surface and a second surface opposite to each other, a touchpad area disposed on the first surface of the substrate for generating a touch signal according to a touch situation, an antenna disposed on the first surface and/or the second surface of the substrate for receiving and transmitting a Radio-Frequency signal, and a control module disposed on the second surface of the substrate and coupled to the touchpad area and the antenna for generating a touch control signal according to the touch signal and generating an identification signal according to the Radio-Frequency signal to the computer system. | 12-26-2013 |
20150029073 | Transmission Device and Near Field Communication Device Using the Same - A transmission device for a near field communication (NFC) device includes a matching circuit, a connecting interface with a first width for connecting an operating circuit of the NFC device, a first transmission line electrically connected between an antenna of the NFC device and the matching circuit, and a second transmission line electrically connected between connecting interface and the matching circuit, including an increasing width portion and a constant width portion, wherein a width of the second transmission increases from the first width to a second width within the increasing width portion and keeps the second width within the constant width portion, wherein the second width is greater than and related to the first width. | 01-29-2015 |
20150145746 | Loop Antenna - A loop antenna is provided, which includes a first loop section, a second loop section and a third loop section. The first loop section surrounds and defines an empty area. The second loop section surrounds and connects the first loop section, and an annular groove is formed between the first loop section and the second loop section. The third loop section surrounds and connects the second loop section. The width of a gap between the third loop section and the second loop section is smaller than the width of the annular groove. | 05-28-2015 |
Chih-Hsiang Peng, Hsinchu TW
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20130181846 | METER APPARATUS, METERING NETWORK, AND METERING METHOD THEREOF - A meter apparatus, a metering network, and a metering method thereof are provided. The meter apparatus includes a pulse generator, an optical sensor, a spinning disc, and a magnetic sensor. The pulse generator is configured to generate a number of pulses proportional to an amount of a consumed resource. The optical sensor is configured to detect the number of pulses to generate a first signal, and transmit the first signal to a meter reader. The spinning disc is configured to produce an amount of rotation proportional to the amount of the consumed resource. The magnetic sensor is configured to detect the amount of the rotation to generate a second signal, and transmit the second signal to the meter reader. | 07-18-2013 |
20130187807 | ANTENNA APPARATUS AND ANTENNA SWITCH CIRCUIT - An antenna device and an antenna switch circuit are provided. The antenna device comprises a first antenna, an antenna detection circuit, a switch control circuit, and a controller. The first antenna is configured to transmit an RF signal. The antenna detection circuit comprises an inductor configured to detect a second antenna. The switch control circuit is coupled to the antenna detection circuit and configured to generate a first control signal indicative of the presence of the second antenna upon the detection thereof. The controller is coupled to the first antenna, the antenna detection circuit and the switch control circuit, and configured to receive the first control signal and connect to the second antenna when the first control signal indicates the presence of the second antenna. | 07-25-2013 |
Chih-Ping Peng, Hsinchu TW
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20090139645 | Method for maintaining vacuum-tight inside a panel module and structure for the same - This invention provides a method for maintaining vacuum of a panel module and a structure of the panel module. A sealing material is suspended inside the panel module right above an exhaust opening of the panel module connecting with an exhaust tube. After exhausting the inside of the panel module, the sealing material is heated and molten so as to drop down to seal the exhaust tube. As such, the panel module becomes vacuum-tight. During a subsequent annealing process to heat the exhaust tube to its melting temperature, ambient air is prohibited from flowing into the panel module. | 06-04-2009 |
Chih-Yu Peng, Hsinchu TW
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20090268118 | ACTIVE DEVICE ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL, ELECTRO-OPTICAL DEVICE, METHOD FOR FABRICATING THE SAME, AND METHODS FOR DRIVING THE SAME - An active device array substrate is provided. The active device array substrate includes a plurality of pixel units. Each of the pixel units includes a first active device, a first scan line, a second active device, a second scan line, a data line, a common line, and a pixel electrode. The first scan line is electrically connected to a first gate of the first active device. The second scan line is electrically connected to a second gate of the second active device. The data line is electrically connected to a first source of the first active device. The common line is electrically connected to a second source of the second active device. The pixel electrode is electrically connected to a first drain of the first active device and a second drain of the second active device. | 10-29-2009 |
20120154344 | ELECTRIC PAPER DISPLAY APPARATUS - An electric paper display apparatus includes a substrate, a display layer and a protective layer. The display layer is disposed on the substrate. The protective layer is disposed on the display layer. The protective layer includes a bottom surface facing to the display layer and a plurality of color filter patterns disposed on the bottom surface. It does not need to dispose a color filter substrate on the protective layer of the electric paper display apparatus, so a cost and a thickness of the electric paper display apparatus can be reduced. | 06-21-2012 |
Chin-Chun Peng, Hsinchu TW
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20140145982 | TOUCH PANEL AND A CONTROL METHOD THEREOF - A touch panel control method applied to a touch panel including at least one antenna and a touch sensing structure having a plurality of touch sensing elements is provided. In the touch panel control method, a scan signal is transmitted to at least one of the plurality of touch sensing elements, and a sensing signal sensed by at least one of the plurality of touch sensing elements is received. Whether the at least one antenna starts operating is detected by a control sensor, and if so, operation of a first plurality of touch sensing elements of the plurality of touch sensing elements is stopped, wherein each of the first plurality of touch sensing elements overlaps the at least one antenna. | 05-29-2014 |
Ching-Nen Peng, Hsinchu TW
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20120097944 | TEST STRUCTURES FOR THROUGH SILICON VIAS (TSVs) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) - A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded. | 04-26-2012 |
20130196458 | METHOD OF TESTING THROUGH SILICON VIAS (TSVS) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) - In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded. | 08-01-2013 |
20140043148 | THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD FOR WIRELESS INFORMATION ACCESS THEREOF - A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure. | 02-13-2014 |
20140266281 | TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE - A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body. | 09-18-2014 |
Ching-Tsu Peng, Hsinchu TW
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20110054103 | Fast Heat-up Thermoplastic Polymer Composition and Preparation Thereof - Disclosed herein is a thermoplastic polymer composition which has the beneficial combination of improved heat-up rates, high clarity, and low haze. Bottles are made from the bottle preforms by reheating the bottle preforms, wherein the bottle preforms include metal additives, and the blow moulding bottles from the reheated preforms. | 03-03-2011 |
20110105715 | Titanium Oxide Composition and the Application Thereof on Poly-Esterification - The application discloses a Titanium oxide composition and the application thereof. The mentioned Titanium oxide composition comprises Titanium co-precipitate(s), organic acid, diol, and water. According to this application, a catalyzed poly-esterification with said Titanium oxide composition is also disclosed. The mentioned polyesterification comprises a step of adding said Titanium oxide composition into at least one stage selected from slurry stage, esterification stage, and polycondensation stage. | 05-05-2011 |
Ching-Yen Peng, Hsinchu TW
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20120273821 | METHOD FOR PATTERNING AN EPITAXIAL SUBSTRATE, A LIGHT EMITTING DIODE AND A METHOD FOR FORMING A LIGHT EMITTING DIODE - A method for patterning an epitaxial substrate includes: (a) forming an etch mask layer over an epitaxial substrate, and patterning the etch mask layer using a patterned cover mask layer to form the etch mask layer into a plurality of spaced apart mask patterns; and (b) etching the epitaxial substrate that is exposed from the mask patterns, and removing the mask patterns such that the epitaxial substrate is formed with a plurality of spaced apart substrate patterns. | 11-01-2012 |
Chiou-Shian Peng, Hsinchu TW
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20090111208 | COLORS ONLY PROCESS TO REDUCE PACKAGE YIELD LOSS - Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses. | 04-30-2009 |
Chi-Sheng Peng, Hsinchu TW
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20150325585 | METHOD FOR FORMING THREE-DIMENSIONAL MEMORY AND PRODUCT THEREOF - A method for forming a 3D memory is described. A stacked structure including alternately arranged semiconductor layers and insulating layers is formed on a substrate. The stacked structure is patterned into linear stacks in a row direction, wherein each linear stack includes alternately arranged channel layers and linear insulators. An insulating material is filled in between the linear stacks. Damascene openings are formed in the insulating material between each two neighboring linear stacks, wherein each damascene opening exposes a portion of each of the opposite sidewalls of all the channel layers of two neighboring linear stacks. A charge trapping layer is formed. Word lines are formed in the damascene openings. | 11-12-2015 |
20150325668 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a method for fabricating a semiconductor device including the following steps. A silicon-containing conductive layer is formed on a substrate. Then, a dielectric layer is formed around the silicon-containing conductive layer. A portion of the dielectric layer is removed to expose a first sidewall of the silicon-containing conductive layer. A shielding structure is formed on a partial surface of the silicon-containing conductive layer, and the shielding structure exposes at least the first sidewall. A metal layer is formed on the substrate to cover the silicon-containing conductive layer not covered by the shielding structure. A salicide process is performed to form a silicide layer. | 11-12-2015 |
20160099217 | LINE LAYOUT AND METHOD OF SPACER SELF-ALIGNED QUADRUPLE PATTERNING FOR THE SAME - A line layout and a spacer self-aligned quadruple patterning method thereof are provided. The line layout includes a first line, a second line, a third line, and a fourth line. The second line and the third line are disposed between the first line and the fourth line. The first line, the second line, the third line, and the fourth line respectively extend in a first direction. An end segment of the second line and an end segment of the third line respectively include a first protrusion portions that extend in a second direction. The first protrusion portion of the end segment of the second line protrudes toward the first line. The first protrusion portion of the end segment of the third line protrudes toward the fourth line. | 04-07-2016 |
Chung Peng, Hsinchu TW
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20090185371 | Backlight Module Unit and Backlight Module - A backlight module unit and a backlight module are provided. The backlight module unit includes a first light source, a second light source, and an optical barrier. A light source interval is defined between the first light source and the second light source, while a barrier interval is defined between the optical barrier and the second light source. Because the barrier interval is substantially shorter than a half of the light source interval, the backlight module unit mixes the light evenly, and prevents the dark bands from forming due to the disposition of the optical barrier. Thereby, the backlight module that comprises the plural aforesaid backlight units will have no dark bands, mix light evenly, and be thin overall. | 07-23-2009 |
Chung-Nan Peng, Hsinchu TW
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20140252296 | RESISTIVE RANDOM-ACCESS MEMORY - The present invention relates to a resistive random-access memory, including: a bottom electrode; a resistive switch layer disposed on the bottom electrode, including a first switch layer, a second switch layer, and a filament path control layer, wherein the first switch layer is interposed between the bottom electrode and the filament path control layer, and the filament path control layer is interposed between the first switch layer and the second switch layer; and a top electrode disposed on the second switch layer, wherein the filament path control layer includes one or more micro-pores. The present invention also relates to a memory array which includes a substrate and a plurality of the above-mentioned resistive random access memories, wherein the resistive random access memories are disposed on the substrate. | 09-11-2014 |
Chun-Hong Peng, Hsinchu TW
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20140110777 | TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF - A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate. | 04-24-2014 |
20150318366 | FABRICATING METHOD OF TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate. | 11-05-2015 |
Chun-Yen Peng, Hsinchu TW
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20120305965 | LIGHT EMITTING DIODE SUBSTRATE AND LIGHT EMITTING DIODE - A light emitting diode (LED) substrate includes a sapphire substrate which is characterized by having a surface consisting of irregular hexagonal pyramid structures, wherein a pitch of the irregular hexagonal pyramid structure is less than 10 μm. A symmetrical cross-sectional plane of each of the irregular hexagonal pyramid structures has a first base angle and a second base angle, wherein the second base angle is larger than the first base angle, and the second base angle is 50° to 70°. This LED substrate has high light-emitting efficiency. | 12-06-2012 |
Ci-Guang Peng, Hsinchu TW
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20090185371 | Backlight Module Unit and Backlight Module - A backlight module unit and a backlight module are provided. The backlight module unit includes a first light source, a second light source, and an optical barrier. A light source interval is defined between the first light source and the second light source, while a barrier interval is defined between the optical barrier and the second light source. Because the barrier interval is substantially shorter than a half of the light source interval, the backlight module unit mixes the light evenly, and prevents the dark bands from forming due to the disposition of the optical barrier. Thereby, the backlight module that comprises the plural aforesaid backlight units will have no dark bands, mix light evenly, and be thin overall. | 07-23-2009 |
Du-Zen Peng, Hsinchu TW
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20090267501 | ACTIVE MATRIX DISPLAY AND IMAGE DISPLAY SYSTEM USING SAME - The present invention relates to an active matrix display and an image display system using the active matrix display. The image display system includes the active matrix display and a power supply apparatus. The active matrix display includes an active matrix substrate, a reflective layer and a sidewall-protective structure. The reflective layer is formed above the active matrix substrate and has first and second surfaces. The second surface faces the active matrix substrate. The sidewall-protective structure is formed above the active matrix substrate and surrounds the sidewalls of the reflective layer adjacent to the first and second surfaces. | 10-29-2009 |
Hsin-Yuan Peng, Hsinchu TW
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20100063649 | Intelligent driving assistant systems - The invention discloses an intelligent driving assistant system applied to a handheld device. The invention can detect more than one safety mode including lane departure detection, lost-cargo detection, detecting front-object under driving condition, detecting side-object under driving condition and detecting back-object under driving condition, also the invention can mention alarm according to the detection results from different modules. Finally the invention can store the real-time image according to the detection results from different modules, and then transfer the related information to other places for real-time notice with matching the information from the GPS system and the digitized map. | 03-11-2010 |
20120324382 | User Interface Adjusting Method and Electronic Device Using the Same - A user interface adjusting method for an electronic device is disclosed. The electronic device is capable of displaying a user interface including a plurality of selecting objects. The user interface adjusting method includes calculating amounts of the plurality of selecting objects being selected, and adjusting locations of the plurality of selecting objects within the user interface according to the amounts of the plurality of selecting objects being selected. | 12-20-2012 |
Hsu-Hsia Peng, Hsinchu TW
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20150360020 | IMAGING SYSTEM OF MICROBUBBLE THERAPY AND IMAGE EVALUATION METHOD USING THE SAME - An imaging system of microbubble therapy cooperated with an ultrasound device for monitoring a cavitation on microbubbles in a vessel of an affected part is disclosed in the present invention, in which the cavitation is occurred by applying an ultrasound to disrupt the microbubbles. The system comprises an image acquiring module and a controlling module. The image acquiring module comprises at least one magnetic resonance device for acquiring a plurality of magnetic resonance images of the cavitation, and the controlling module provided for controlling an acquiring time of the magnetic resonance device and an irradiation time of the ultrasonic device through a controlling mode. An image evaluation method using the same is also disclosed herein and comprises steps as the following. First, injecting the microbubbles into the vessel of the affected part is performed. And then, a plurality of magnetic resonance images by a magnetic resonance device and in an acquiring time is acquired. The microbubbles are irradiated for an irradiation time by an ultrasound. Finally, changes of the magnetic resonance images will be monitored, in which an irradiation path of the ultrasound may be perpendicular to a direction of flow in the vessel and the irradiation time is within the acquiring time. | 12-17-2015 |
Huang-Tse Peng, Hsinchu TW
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20130176047 | TEST DEVICE FOR WIRELESS ELECTRONIC DEVICES - A test device for wireless electronic devices includes a metal casing, a RF-absorbing material, a measurement antenna, and an impedance adjustment module. The impedance adjustment module includes a dielectric layer, a microstrip line, and a slot line, wherein the slot line is electrically connected to the measurement antenna. The microstrip line and the slot line are disposed on two opposite sides of the dielectric layer and respectively include a first body and a second body, which are parallel to each other. | 07-11-2013 |
20150200458 | Wireless Communication Device - A wireless communication device includes an antenna for receiving a receiving signal and including a radiator whose input impedance is inductively centralized, a tunable matching circuit coupled to the antenna for adjusting a matching of the antenna according to a control signal, and a radio-frequency processing circuit coupled to the tunable matching circuit, for determining whether to adjust the matching of the antenna according to a receiving band and a transmitting band corresponding to the receiving signal to generate the control signal to the tunable matching circuit, wherein the tunable matching circuit adjusts the matching of the antenna to optimize the matching of the antenna in the receiving band and the transmitting band. | 07-16-2015 |
20150200646 | Wireless Communication Device and Method of Adjusting Antenna Matching - A wireless communication device includes a diversity antenna operating in a receiving frequency band to receive a receiving signal in the reception frequency band, a tunable matching circuit for adjusting a matching of the diversity antenna according to a control signal, a detection circuit for detecting a wireless communication system corresponding to the receiving signal to generate a detection result, wherein the detection result indicates an antenna configuration and a transmission frequency band corresponding to the wireless communication system, and a radio-frequency processing circuit for determining whether to adjust the matching of the diversity antenna to weaken antenna performance of the diversity antenna in both or one of the transmission frequency band and the reception frequency band according to the antenna configuration so as to improve an isolation between the diversity antenna and a main antenna. | 07-16-2015 |
20150333390 | Wideband Antenna and Wireless Communication Device - A wideband antenna includes a first radiator formed as a part of a metal frame for resonating a first signal component of a radio-frequency signal, a second radiator disposed within an area enclosed by the metal frame for resonating a second signal component of the radio-frequency signal, and a feed terminal electrically connected between the second radiator and a ground for feeding the radio-frequency signal, wherein there is a distance between the first and second radiators such that a coupling effect is induced between the first and second radiators, which allows the first signal component being fed from the second radiator into the first radiator via the coupling effect. | 11-19-2015 |
I-Hsuan Peng, Hsinchu TW
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20090155988 | ELEMENT OF LOW TEMPERATURE POLY-SILICON THIN FILM AND METHOD OF MAKING POLY-SILICON THIN FILM BY DIRECT DEPOSITION AT LOW TEMPERATURE AND INDUCTIVELY-COUPLED PLASMA CHEMICAL VAPOR DEPOSITION EQUIPMENT THEREFOR - A low temperature poly-silicon thin film element, method of making poly-silicon thin film by direct deposition at low temperature, and the inductively-coupled plasma chemical vapor deposition equipment utilized, wherein the poly-silicon material is induced to crystallize into a poly-silicon thin film at low temperature by means of high density plasma and substrate bias voltage. Furthermore, the atom structure of the poly-silicon thin film is aligned in regular arrangement by making use of the induction layer having optimal orientation and lattice constant close to that of the silicon, thus raising the crystallization quality of the poly-silicon thin film and reducing the thickness of the incubation layer. | 06-18-2009 |
Jung-Huei Peng, Hsinchu TW
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20160096722 | Cap and Substrate Electrical Connection at Wafer Level - A cap and substrate having an electrical connection at a wafer level includes providing a substrate and forming an electrically conductive ground structure in the substrate and electrically coupled to the substrate. An electrically conductive path to the ground structure is formed in the substrate. A top cap is then provided, wherein the top cap includes an electrically conductive surface. The top cap is bonded to the substrate so that the electrically conductive surface of the top cap is electrically coupled to the path to the ground structure. | 04-07-2016 |
Jyi-Ching Peng, Hsinchu TW
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20120073309 | THERMOELECTRIC DRINKING APPARATUS AND THERMOELECTRIC HEAT PUMP - A thermoelectric drinking apparatus has a feeding pipe, a cooling-gain circulating loop, a heating-gain circulating loop, an outlet pipe, and a thermoelectric heat pump. The thermoelectric heat pump has a cooling unit attached to the cold side of a thermoelectric chip, which has a cooling channel in its interior, and a heating unit attached to the hot side of the thermoelectric chip and provided with a heating channel in its interior. The feeding pipe conducts fluid into the cooling channel and the heating channel respectively. The cooling-gain and heating-gain circulating loop respectively cause fluids in the cooling channel and heating channel to create circular flows, such that the cold side and hot side of the thermoelectric chip respectively cool and heat the fluids via the cooling channel and heating channel. The outlet pipe discharges the cooled and/or heated fluids respectively from the cooling-gain circulating loop and heating-gain circulating loop. | 03-29-2012 |
Kang-Yung Peng, Hsinchu TW
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20090066238 | Electroluminescent materials grafted with charge transport moieties having graded ionization potential or electrophilic property and their application in light-emitting diodes - This invention provides new electroluminescent materials such as a conjugated polymer or a phosphorescent organometallic complex, which are grafted with multiple charge transport moieties with graded ionization potential or electrophilic property. The charge transport moieties can be all hole transport moieties or all electron transport moieties. The emissive electroluminescent materials covering the full visible range can be prepared. Organic light emitting diodes prepared with these materials can be used as indicators, light source and display for cellular phones, digital camera, pager, portable computer, personal data acquisition (PDA), watch, hand-held videogame, and billboard, etc. | 03-12-2009 |
Kuo-Cheng Peng, Hsinchu TW
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20110030670 | PORTABLE ANTI-SCORCHING ROASTING CAN - A portable anti-scorching roasting can includes a can body, at least one segregating cage, a cover, a pivoting element, a combining element, and a handle. The can body has an open end and a containing space. The segregating cage has a plurality of openings. The segregating cage located in the containing space is used to contain the foodstuff. The pivoting element is located between the cover and the can body. By using the pivoting element, user can open or close the cover at the open end of the can body. The combining element is located between the pivoting element and the can body. By using the combining element, the pivoting element, which is connected to the cover, is combined into the can body. The handle has a connecting portion which is connected with the cover, and has a handle grip which is made of thermal insulating material. | 02-10-2011 |
20110239356 | URINE BOTTLE ADAPTER - A urine bottle adapter is provided. The urine bottle adapter has a hollow body which meets human ergonomics. The hollow body includes an open end and a flow guiding hole opposite to the open end. The open end of the urine bottle adapter is compliant with ergonomics, so that it can comfortably cover the user's private part. There are internal screw threads in the flow guiding hole. By means of the internal screw threads, an empty PET bottle can be screwed into the flow guiding hole, thus the empty PET bottle would be used to hold the urine. Therefore, the urine bottle adapter could transform an empty PET bottle into a urine bottle. The empty PET bottle can be easily washed and used repeatedly. | 10-06-2011 |
Kuo-Ta Peng, Hsinchu TW
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20130259324 | Method for face recognition - A method for face recognition is provided with collecting a match facial image; retrieving a reference image from image records of a database or an input image; selecting one or more facial features from each of the match facial image and the reference image; obtaining at least one match facial feature and a match deviation of the reference image corresponding to the facial features of the match facial image; creating a match geometric model and a reference geometric model; obtaining a model deviation by comparing the match geometric model and the reference geometric model; and employing a match deviation and a model deviation to obtain a recognition score based on a predetermined rule. The method involves a two-way face recognition by integrating facial features of block matching with geometric model comparison. It employs relationship of match deviation and model deviation. | 10-03-2013 |
Lung-Han Peng, Hsinchu TW
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20120264246 | Method of Selective Photo-Enhanced Wet Oxidation for Nitride Layer Regrowth on Substrates - Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation. | 10-18-2012 |
20120264247 | Method of Separating Nitride Films from the Growth Substrates by Selective Photo-Enhanced Wet Oxidation - Various embodiments of the present disclosure pertain to separating nitride films from growth substrates by selective photo-enhanced wet oxidation. In one aspect, a method may transform a portion of a III-nitride structure that bonds with a first substrate structure into a III-oxide layer by selective photo-enhanced wet oxidation. The method may further separate the first substrate structure from the III-nitride structure. | 10-18-2012 |
20130228807 | METHOD OF SEPARATING NITRIDE FILMS FROM GROWTH SUBSTRATES BY SELECTIVE PHOTO-ENHANCED WET OXIDATION AND ASSOCIATED SEMICONDUCTOR STRUCTURE - Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a semiconductor structure may comprise: a first substrate structure; a III-nitride structure bonded with the first substrate structure; a plurality of air gaps formed between the first substrate structure and the III-nitride structure; and a III-oxide layer formed on surfaces around the air gaps, wherein a portion of the III-nitride structure including surfaces around the air gaps is transformed into the III-oxide layer by a selective photo-enhanced wet oxidation, and the III-oxide layer is formed between an untransformed portion of the III-nitride structure and the first substrate structure. | 09-05-2013 |
20140131750 | METHOD OF SELECTIVE PHOTO-ENHANCED WET OXIDATION FOR NITRIDE LAYER REGROWTH ON SUBSTRATES AND ASSOCIATED STRUCTURE - Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation. | 05-15-2014 |
20140252308 | METHOD OF SELECTIVE PHOTO-ENHANCED WET OXIDATION FOR NITRIDE LAYER REGROWTH ON SUBSTRATES AND ASSOCIATED STRUCTURE - Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation. | 09-11-2014 |
Mei-Chih Peng, Hsinchu TW
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20100177266 | Optical film - The present invention provides an optical film with functions of light collimating, light polarization for brightness enhancement and limiting viewing angle and a method for preparing the same. The optical film includes a plurality of layers of a cholesteric liquid crystal film bound together via an optical adhesive and a quarter-wavelength retardation plate bound with the cholesteric liquid crystal film via the optical adhesive. Therein, at least one layer of the cholesteric liquid crystal film has a polarized separated wavelength range covering the wavelength range of visible light of three primary colors of red, green and blue. | 07-15-2010 |
Mei-Fang Peng, Hsinchu TW
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20130049197 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer. | 02-28-2013 |
20130049198 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor package structure is provided. A chip is provided. An active surface of the chip is disposed on a carrier. A molding compound is formed on the carrier with a metal layer disposed thereon. The metal layer has an upper and lower surface, multiple cavities formed on the upper surface and multiple protrusions formed on the lower surface and corresponding to the cavities. The protrusions are embedded in the molding compound. The metal layer is patterned to form multiple pads on a portion of the molding compound. The carrier and the molding compound are separated. Multiple through holes are formed on the molding compound exposing the protrusions. A redistribution layer is formed on the molding compound and the active surface of the chip. Multiple solder balls are formed on the redistribution layer. A portion of the solder balls are correspondingly disposed to the pads. | 02-28-2013 |
Ming-Chih Peng, Hsinchu TW
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20160061875 | CIRCUIT AND METHOD FOR TESTING RF DEVICE AND RF DEVICE WITH BUILT-IN TESTING CIRCUIT - In a testing circuit performing a testing operation to detect an RF circuit characteristic, a first filter unit is provided, having a first external terminal electrically coupled to a testing signal and a second external terminal electrically coupled to an RF circuit of the RF device. The first filter unit is configured to allow the testing signal to enter the RF circuit while blocking an RF signal transmitted in the RF circuit from entering the testing circuit. In addition, a testing-result informing unit is provided, having an external input electrically coupled to the first external terminal, and generating an informing signal, which indicates a condition of the RF circuit according to an electric level at the external input. | 03-03-2016 |
Ming-Chung Peng, Hsinchu TW
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20080242798 | Anti-leaking cartridge and anti-leaking ink - The present invention is generally related to an anti-leaking cartridge and anti-leaking ink. The anti-leaking ink comprises: an organic solvent, which is selected from the group consisting of diethylene glycol, triethylene glycol, triethanolamine amine extra pure, polyethylene glycol 200, and ethylene glycol and functions with at least one seal member for avoiding leakage; at least one dye dissolved in the organic solvent; a buffer solution maintaining the pH value of the anti-leaking ink in between 6.0 to 8.0; an antibacterial avoiding that the properties of the ink is changed; surfactant, which homogenizes the aquas of ink and the organic solvent; and de-ionized water. | 10-02-2008 |
20100201761 | UNINTERRUPTED INK SUPPLY SYSTEM - An uninterrupted ink supply system is provided, including a main cartridge connected to a printer, a connection device having an automatic airflow control structure and installed on said main cartridge, and a replenishment cartridge for connecting to the connection device. The replenishment cartridge is connected to the connection device, and is able to refill the ink into the main cartridge, and automatically stop refilling when the ink level reaching a specific height and start refilling again when ink level below a specific height. When the replenishment cartridge is removed for refilling when the ink is used up, the main cartridge still contains ink so that the printing will not be suspended. | 08-12-2010 |
20110141210 | INK CARTRIDGE APPARATUS FOR CONTINUOUSLY SUPPLYING INK - An ink cartridge apparatus for continuously supplying ink is provided, including a connection device, an exposed chip socket and a filtering device on an ink cartridge main body. The connection device is for connecting to an ink bottle and the filtering device is for filtering the impurity from the ink flowing from the ink bottle into ink cartridge main body. The exposed chip socket is for the user to replace the chip more conveniently. With the ink supply mechanism of ink bottle into ink cartridge main body, the ink cartridge main body can maintain good ink quality and when the threshold set by the chip is exceeded, the replacement of the chip can be done without removing the entire ink cartridge from the printer so as to achieve the object of continuously supplying ink. | 06-16-2011 |
Ming-Tsan Peng, Hsinchu TW
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20120326553 | ELECTROMAGNETIC VARIABLE-SPEED MOTOR TECHNICAL FIELD - An electromagnetic variable-speed motor includes a rotor having a plurality of permanent magnet structures, a stator disposed on the same axis as the rotor and having a plurality of teeth and a plurality of slots, and a variable-speed module disposed on the same axis as the rotor and the stator and at a position between the rotor and stator. Therein, the pole number of the variable-speed module no greater than the number of the slots such that the variable-speed module can be completely integrated with the stator, thereby providing a simplified yet strengthened structure which requires less components and fabrication costs than the prior art. | 12-27-2012 |
20130306829 | SUN-CHASING DEVICE - A sun-chasing device is provided, including a base, a first transmitter disposed on the base, a second transmitter, a support, a carrier pivotally connected to the support for carrying a solar module, a first supporting component pivotally connected to the first transmitter and the carrier, and a second supporting component pivotally connected to the second transmitter and the carrier. The sun-chasing device has great rigidity and carrying ability against strong wind, and has great precision and rotation angle, such that a solar plate can precisely aim at sun for long time and thus the efficiency of a solar module is significantly increased. | 11-21-2013 |
Peng-Chun Peng, Hsinchu TW
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20090231685 | OPTICAL AMPLIFIER FOR TUNING TRANSMISSION TIME OF OPTICAL SIGNAL - The present invention relates to a technique for tuning the transmission time of optical signal, which adopts an optical amplifier with a bending structure for enhancing the tunable time of optical signal. The effect of tunable time of optical signal can be achieved by adjusting the gain of the optical amplifier. | 09-17-2009 |
Po Hsuan Peng, Hsinchu TW
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20110315841 | Mounting Assembly - A mounting assembly is configured in a case having an opening and a door panel. The door panel is pivoted to the case so as to cover the opening or uncover the opening by removing the door panel. The mounting assembly includes at least one fixing rod, a stopper member, at least one elastic member and an actuator. The fixing rod is disposed on one inner side of the case adjacent to the opening. The stopper member and the elastic member are movably disposed on the fixing rod. The actuator is disposed on the door panel. When the door panel covers the opening, the actuator is incorporated with the stopper member, such that the stopper member shields the opening, so as to avoid an object moving around or away from the case through the opening. | 12-29-2011 |
Shen-Yu Peng, Hsinchu TW
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20140112493 | APPARATUS FOR DIFFERENTIAL INTERPOLATION PULSE WIDTH MODULATION DIGITAL-TO-ANALOG CONVERSION AND OUTPUT SIGNAL CODING METHOD THEREOF - A differential interpolation pulse width modulation (iPWM) digital to analog converter is provided, including an iPWM for generating differential pulse from an input digital audio data stream, a power driver for providing energy to a terminal load and a filter for removing unwanted harmonic signal to reconstruct analog signal, wherein the iPWM further includes a PWM pulse generator to convert the digital input numerical code to a series of time domain pulse width; an interpolation unit to increase the time domain resolution of the pulse width; a self-calibration unit to maintain the pulse-width accuracy of the interpolation unit; a differential pulse width generator to convert series of PWM pulse into voltage and time domain differential form. | 04-24-2014 |
Shiang-Hau Peng, Hsinchu TW
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20110111552 | Method for forming organic layers of electronic devices by contact printing - A method for forming organic layers of electronic devices by contact printing is disclosed, which comprises: (A) providing a substrate, which has an electrode formed thereon; (B) coating an organic material ink onto a mold; (C) applying the ink-coated mold onto the substrate, to transfer the organic material ink onto the electrode of the substrate and then to form an organic layer; and (D) forming another electrode on the organic layer. In addition, after the step (C) is completed, the steps (B) to (C) can be repeated once or several times to form series of organic layers, if needed. | 05-12-2011 |
Shu-Fen Peng, Hsinchu TW
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20120258176 | NANOPARTICLES FOR PROTEIN DRUG DELIVERY - The invention discloses particulate complexes composed of chitosan, poly-glutamic acid, and at least one bioactive agent, wherein equal moles of the positively charged chitosan and the negatively charged poly-glutamic acid substrate form an electrostatic network enabling improved loading the bioactive agent. | 10-11-2012 |
Tien-Haw Peng, Hsinchu TW
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20110002097 | Portable Electronic Device - A portable electronic device includes a shell, a control circuit, a display panel and at least a bi-stability display module. The shell has an opening and an accommodating cavity in two different surfaces. The control circuit includes a first information transmission unit. The control circuit and the display panel are disposed in the shell. The display panel is electrically connected to the control circuit. The display panel has a display surface exposed from the opening. The bi-stability display module is detachably disposed in the accommodating cavity and selectively electrically connected to the control circuit. The bi-stability display module includes a second information transmission unit for communicating with the first information transmission unit and a bi-stability display for displaying the information received by the second information transmission unit. The bi-stability display module can display when the control circuit is closed. The power-consumption of the portable electronic device may be decreased. | 01-06-2011 |
20110096000 | TOUCH STRUCTURE AND TOUCH DISPLAY APPARATUS COMPRISING THE SAME - A touch structure and a touch display apparatus comprising the same are provided. The touch display apparatus has a touch controller electrically connected to the touch structure. The touch structure comprises a display panel with a display surface and a sense assembly. The sense assembly is disposed on a surface opposite to the display surface and electrically connected to the touch controller to generate a touch signal while the display surface of the display panel is touched so that the touch controller may act according to the touch signal. | 04-28-2011 |
20130229329 | REPLACEABLE DISPLAY SYSTEM - A replaceable display system includes a display back plate having a driving array substrate, a front panel laminate, and a display region, a controller, and an image film. The front panel laminate is located on the driving array substrate and includes a transparent substrate and a display medium layer sandwiched between the driving array substrate and the transparent substrate. The display region is located on the front panel laminate and includes a plurality of sub-display regions. Each of the sub-display regions is displayed as a bright face or a dark face by the display medium layer. The controller is electrically connected to the display back plate to control each of the sub-display regions to display as the bright face or the dark face. The image film is detachably located on the display region and includes a light transmissive pattern portion aligned with at least one of the sub-display regions. | 09-05-2013 |
Wei-Chung Peng, Hsinchu TW
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20110142173 | RECEIVERS AND SYMBOL DECODERS THEREOF - A receiver capable of decoding a symbol based on information on a previous symbol, the symbol and a next symbol in a Gaussian frequency shift keying (GFSK) communication system is provided. The receiver includes a discriminator to generate a symbol for each bit in a bit sequence, a first lookup table (LUT) to store a number of bit patterns and mapping patterns, wherein each of the bit patterns is in the form of a set of consecutive bits in the bit sequence and corresponds to a respective one of the mapping patterns, and wherein each of the mapping patterns includes a set of entries and each of the entries results from an operation of attribute values at a sample time in the waveform of a symbol, a calculator to receive a set of consecutive symbols from the discriminator and calculate a distance value between the set of consecutive symbols and each of the mapping patterns, and a comparator to identify one of the mapping patterns with a minimum distance value by comparing among the distance values from the calculator. | 06-16-2011 |
Wei-Yuan Peng, Hsinchu TW
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20080284817 | MAINTENANCE STATION OF INKJET PRINTER - A maintenance station of inkjet printer includes a supporter, an ink cup pivoted on the supporter and configured to receive waste ink, a driver and a preventing arm. The ink cup has a circular board and a ring. The circular board is pivoted on the supporter. The ring has a belt fixed on the outer edge of the circular board and a plurality of elastic arms. Each of the elastic arms has a base extended vertically from the belt and an inclined portion bent from the end of the base inclinedly. The driver is configured to push the inclined portion to rotate the ink cup. The preventing arm is configured to press the inclined portion to permit the ink cup to be rotated and push the inclined portion to prevent the ink cup from being rotated. | 11-20-2008 |
20090001655 | PAPER FEED APPARATUS FOR DUPLEX PRINTING APPARATUS - A paper feed apparatus includes a gate, an actuator, a transmission, a pickup device, a reversing device, a paper feed device. The gate has a rack defined at one end of the gate and a resilient arm connecting to the outer portion of the rack. The resilient arm has a plurality of external teeth. The actuator has a pickup gear with a disc-shaped body, an external wheel connecting to the outside of the body and an external gear connecting to the outside of the external wheel. A receiving passage is defined through the pickup gear along the axis thereof. The receiving passage includes a holding hole at one side of the receiving passage that is near to the rack. The resilient arm is inserted into the receiving passage with the external teeth abutting against the inner surface of the holding hole. | 01-01-2009 |
20090040265 | INK STORING BOX - An ink-storing box includes a container, a cover covering on the container and a lock gate. The cover defines at least one communicating hole therein. The lock gate includes a base board movable arranged between the cover and the container and a drive portion located on the base board, the base board defining a cooperation hole therein. The lock gate is set between the cover and the container for allowing the hole of the cover communicating with the interior of the container or shielding the interior of the container from being exposed through the hole of the cover. Thereby the ink-storing box of the present invention can receive the ink jetted from the ink box and prevent the evaporation of the ink. | 02-12-2009 |
20090044586 | GEAR-ROLLING APPARATUS - A gear-rolling apparatus includes two gear units and a base. Each gear unit has a rolling portion, a rolling shaft extends from the rolling portion, a clicking column and two location columns extend from edges of a free end of the rolling shaft along an axle direction of the rolling shaft. The clicking column and the two location columns are spaced out from each other to form three grooves therebetween, a clicking clasp extends inward from the top of the clicking column. The clicking clasp has an inclined inner surface which inclines inward from top to bottom. The two rolling shafts are inserted into the hole of the base, the clicking column of one of the rolling shafts mates the groove opened between the location columns of the other rolling shaft, the location columns of one of the rolling shafts mate the grooves opened between the clicking column and the location columns of the other rolling shaft respectively, bottom surfaces of the two clicking clasps are against each other. | 02-19-2009 |
20090091076 | AUTO DOCUMENT FEEDER - An auto document feeder cooperated with an image processing machine defines a feeding path and has a base, a frame and a sensor device. The base has a background under the feeding path. The frame is mounted on the base. The sensor couples with the frame and has a sensor arm. The sensor arm has an optical sensor located in the feeding path and faced to the background of the base. The sensor device recognizes a sheet is present in the feeding path or not by that the optical sensor recognizes the energy of the light reflected from the background and the sheet. The sensor device also recognizes characteristic of the sheet by that the optical sensor recognizes the energy of the light reflected from the sheet. Therefore, the image processing machine executes different processes for the sheet according to the characteristic of the sheet. | 04-09-2009 |
20090110437 | DUPLEX DOCUMENT FEEDER - A duplex document feeder defines a feeding path. A charging means, a guiding plate equipped with elastic force and a feeding means are located along the feeding path. A driver means provides drive source to the charging means and the inverting means. The guiding plate blocks up the feeding path while the feeding path is empty. The charging means charges a document into the feeding path. The guiding plate is pressed out of the feeding path by the document conveyed via the charging means. Therefore, the document may be conveyed through the feeding path. While the document is conveyed to the feeding means, the guiding plate returns to block up the feeding path via elastic force thereof. | 04-30-2009 |
20090256883 | MAINTENANCE STATION OF AN INKJET PRINTER - A maintenance station of an inkjet printer mounted in a housing of the inkjet printer includes an ink cup rotationally and slidably coupled to the housing about/along an axis of rotation. The ink cup has a basic plate and a columnar rim around the basic plate. The columnar rim respectively defines a plurality of stopping ratchets and driving ratchets with the same gradient direction at a bottom and top thereof. A moving body is slidably disposed in the housing of the inkjet printer. An actuator movably disposed in the moving body moves together with the moving body, a tail of the actuator stretches out from the moving body for matching with the driving ratchets to rotate the ink cup. A plurality of housing ratchets are disposed in the housing of the inkjet printer and arranged into a ring for matching with the stopping ratchets to prevent the ink cup reversion. | 10-15-2009 |
Yan-Hua Peng, Hsinchu TW
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20090051341 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit includes a PTAT current generating circuit for generating a PTAT current; a CTAT circuit generating circuit for generating a CTAT current; a node for receiving the PTAT current and the CTAT current; and, a first resistor connected between the node and a ground, wherein a reference voltage is derived from the first resistor when a superposed current of the PTAT current and the CTAT current is flowing through the first resistor. | 02-26-2009 |
Yen Chun Peng, Hsinchu TW
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20140292489 | POSITIONING SYSTEM AND POSITIONING METHOD - A positioning system includes an object storage device, a plurality of RFID (Radio Frequency Identification) tags, an antenna, and an RFID reader. The object storage device includes a plurality of storage vacancies. The RFID tags are respectively disposed in the storage vacancies. The antenna is disposed in the object storage device. The RFID reader detects the RFID tags via the antenna. The RFID reader stores a corresponding relationship between the RFID tags and the storage vacancies. When an object is placed in a specific storage vacancy, the RFID reader determines that a specific RFID tag disposed in the specific storage vacancy is no longer detectable, and determines that the specific storage vacancy is occupied further according to the corresponding relationship. | 10-02-2014 |
Young-Chow Peng, Hsinchu TW
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20130198710 | SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION - A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor. | 08-01-2013 |
20130346935 | SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION - A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor. | 12-26-2013 |
Yuan-Ching Peng, Hsinchu TW
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20110079820 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 04-07-2011 |
20110210393 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 09-01-2011 |
20120322246 | FABRICATION METHODS OF INTEGRATED SEMICONDUCTOR STRUCTURE - A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region. | 12-20-2012 |
20130161650 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 06-27-2013 |
20140197455 | SEMICONDUCTOR SUBSTRUCTURE HAVING ELEVATED STRAIN MATERIAL-SIDEWALL INTERFACE AND METHOD OF MAKING THE SAME - A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate. | 07-17-2014 |
20150115322 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 04-30-2015 |
20150228791 | SEMICONDUCTOR SUBSTRUCTURE HAVING ELEVATED STRAIN MATERIAL-SIDEWALL INTERFACE AND METHOD OF MAKING THE SAME - A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate. | 08-13-2015 |
Yuan Yu Peng, Hsinchu TW
Patent application number | Description | Published |
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20120127129 | Optical Touch Screen System and Computing Method Thereof - An optical touch screen system includes a sensing device and a processing unit. The sensing device includes first and second sensors, each generating an image. The images include the image information of a plurality of objects. The processing unit generates a plurality of candidate coordinates according to the image information and selects a portion of the candidate coordinates as output coordinates according to an optical feature of the image information. | 05-24-2012 |
20130265283 | OPTICAL OPERATION SYSTEM - An optical operation system includes an image sensing apparatus and a processing circuit. The image sensing apparatus is disposed at an edge of an operation plane and includes a first sensing array and a second sensing array. The first sensing array is configured to capture images at a first height above the operation plane and accordingly generate a first output signal. The second sensing array is configured to capture images at a second height above the operation plane and accordingly generate a second output signal; wherein the first height is greater than the second height. The processing circuit is electrically connected to the image sensing apparatus and configured to receive the first output signal and the second output signal and accordingly generate a first control command and a second control command, respectively. | 10-10-2013 |
Yuen Hsin Peng, Hsinchu TW
Patent application number | Description | Published |
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20080214734 | Manufacturing method of ladder-like phosphorus-containing polysilsesquioxanes nanocomposite material - A manufacturing method of ladder-like phosphorus-containing polysilsesquioxanes nanocomposite material is disclosed. The method uses a reaction between ladder-like phosphorus-containing polysilsesquioxanes and modified epoxy. Besides improved char yield and limiting oxygen index, thermal degradation rate of the nanocomposite material is lowered dramatically so that the nanocomposite material possesses excellent flame retardance and thermal stability. Moreover, optical transparency of the nanocomposite material according to the present invention is still good, not being reduced by increased amount of polysilsesquioxanes. Thus the nanocomposite material is applied to decorative paints or protective paints. | 09-04-2008 |
Yung-Chow Peng, Hsinchu TW
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20100020862 | INPUT CONTROL CIRCUIT FOR THE SUMMER OF A DECISION FEEDBACK EQUALIZER - This invention discloses a tap circuit in a summer of a decision feedback equalizer (DFE), the tap circuit comprises a differential pair of received signal lines, a current source having a magnitude being substantially proportional to a tap weight coupled between a first node and a ground, a plurality of NMOS transistors controllably coupled the current source to either one of the received signal lines, and DFE data signals and DEF logic sign signals being coupled only to the gates of the plurality of NMOS transistors, wherein tap circuit can operate at low supply voltage without losing speed. | 01-28-2010 |
20110057826 | MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS), SYSTEMS, AND OPERATING METHODS THEREOF - A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that is capable of generating a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The MEMS is free from including any amplifier between the micro-mechanical structure and the ADC. | 03-10-2011 |
20110090198 | LCD DRIVER - A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit. | 04-21-2011 |
20110090947 | DECISION FEEDBACK EQUALIZERS AND OPERATING METHODS THEREOF - A method for updating a tap coefficient of a decision feedback equalizer is provided. The method includes sampling a first input signal received by a sampler of a decision feedback equalizer. It is determined if an amplitude of the first input signal falls within a range defined between a first predetermined voltage level and a second predetermined voltage level. If the amplitude of the first input signal falls outside the range, a tap coefficient is updated to generate an updated tap coefficient that is fed back to adjust an amplitude of a second input signal received at an input end of the decision feedback equalizer. If the amplitude of the first input signal falls within the range, the tap coefficient is free from being updated. | 04-21-2011 |
20110102086 | INPUT COMMON MODE CIRCUIT - A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level. | 05-05-2011 |
20110215420 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 09-08-2011 |
20110260746 | BUILT-IN SELF-TEST CIRCUIT FOR LIQUID CRYSTAL DISPLAY SOURCE DRIVER - A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range. | 10-27-2011 |
20110279150 | BUFFER OPERATIONAL AMPLIFIER WITH SELF-OFFSET COMPENSATOR AND EMBEDDED SEGMENTED DAC FOR IMPROVED LINEARITY LCD DRIVER - A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range. | 11-17-2011 |
20120126897 | INPUT COMMON MODE CIRCUIT - A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level. | 05-24-2012 |
20120176193 | DRIVER FOR A SEMICONDUCTOR CHIP - A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type transistors connected to a positive power supply line, the source of the n-type transistors connected to a ground power supply line. The gates of the p and n-type transistors connected to a first and second input signals respectively. The drains of the p and n-type transistors connected to the drain wire. The p and n-type transistors arranged so that a difference between a number of n-type transistors connected to the drain wire and a number of p-type transistors connected to the drain wire between the first end of the drain wire and all distances along the drain wire being less than two. | 07-12-2012 |
20120218235 | Systems And Methods Providing Active And Passive Charge Sharing In A Digital To Analog Converter - A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value. | 08-30-2012 |
20130147057 | THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT - Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in | 06-13-2013 |
20130185688 | OVER STRESS VERIFY DESIGN RULE CHECK - Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured. | 07-18-2013 |
20130185689 | METHOD OF AND SYSTEM FOR GENERATING OPTIMIZED SEMICONDUCTOR COMPONENT LAYOUT - A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components. | 07-18-2013 |
20130195142 | SMALL AREA HIGH PERFORMANCE CELL-BASED THERMAL DIODE - A thermal sensing system includes a circuit having a layout including standard cells arranged in rows and columns. First and second current sources provide first and second currents, respectively. The thermal sensing system includes thermal sensing units, first and second switching modules, and an analog to digital converter (ADC). Each thermal sensing unit is configured to provide a voltage drop dependent on a temperature at that thermal sensing unit. The first switching module is configured to select one of the thermal sensing units. The second switching module includes at least one switch controllable by a control signal. The at least one switch is configured to selectively couple the thermal sensing units, based on the control signal, to one of the first and second current sources, via the first switching module. The ADC is configured to convert an analog voltage, provided by the selected thermal sensing unit, to a digital value. | 08-01-2013 |
20130207694 | HIGH SPEED COMMUNICATION INTERFACE WITH AN ADAPTIVE SWING DRIVER TO REDUCE POWER CONSUMPTION - A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator. | 08-15-2013 |
20130285190 | Layout of a MOS Array Edge with Density Gradient Smoothing - A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry. | 10-31-2013 |
20130311957 | SEMICONDUCTOR DEVICE DESIGN SYSTEM AND METHOD OF USING THE SAME - A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information. | 11-21-2013 |
20140007031 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT | 01-02-2014 |
20140042585 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM - This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device. | 02-13-2014 |
20140092939 | Thermal Sensor with Second-Order Temperature Curvature Correction - Some embodiments of the present disclosure relate to a stacked integrated chip structure having a thermal sensor that detects a temperature of one or a plurality of integrated chips. In some embodiments, the stacked integrated chip structure has a main integrated chip and a secondary integrated chip located on an interposer wafer. The main integrated chip has a reference voltage source that generates a bias current. The secondary integrated chip has a second thermal diode that receives the bias current and based thereupon generates a second thermal sensed voltage and a second reference voltage that is proportional to a temperature of the secondary integrated chip. A digital thermal sensor within the main integrated chip determines a temperature of the secondary integrated chip based upon as comparison of the second thermal sensed voltage and the reference voltage. | 04-03-2014 |
20140103494 | Nearly Buffer Zone Free Layout Methodology - The present disclosure relates to a layout arrangement and method to minimize the area overhead associated with a transition between a semiconductor device array and background features. A nearly buffer zone free layout methodology is proposed, wherein an array of square unit cells with a first pattern density value is surrounded by background features with a second pattern density value. A difference between the first pattern density value and second pattern density value results in a density gradient at an edge of the array. Unit cells on the edge of the array which are impacted by a shape tolerance stress resulting from the density gradient are identified and reconfigured from a square shape aspect ratio to a rectangular shape aspect ratio with along axis of the unit cell oriented in a direction parallel to the variation induced shape tolerance stress to alleviate the variation. | 04-17-2014 |
20140146868 | DECISION FEEDBACK EQUALIZERS AND OPERATING METHODS THEREOF - A decision feedback equalizer (DFE) includes a sampler for receiving a first input signal and comparing an amplitude of the first input signal with a first predetermined voltage level and a second predetermined voltage level. The DFE includes a DFE logic circuit for receiving at least one first sign signal based on comparison results, and for selectively updating a tap coefficient based on the at least one first sign signal. The DFE logic circuit is configured to update the tap coefficient when the at least one first sign signal indicates the amplitude of the first input signal is not between the first predetermined voltage level and the second predetermined voltage level. The DFE logic circuit is configured to maintain the tap coefficient when the at least one first sign signal indicates the amplitude of the first input signal is between the first and the second predetermined voltage levels. | 05-29-2014 |
20140159932 | ARRANGEMENT FOR DIGITAL-TO-ANALOG CONVERTER - Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout. | 06-12-2014 |
20140215419 | ANALYTICAL MODEL FOR PREDICTING CURRENT MISMATCH IN METAL OXIDE SEMICONDUCTOR ARRAYS - A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom. | 07-31-2014 |
20140372959 | ANALYTICAL MODEL FOR PREDICTING CURRENT MISMATCH IN METAL OXIDE SEMICONDUCTOR ARRAYS - A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom. | 12-18-2014 |
20150020039 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 01-15-2015 |
20150035568 | TEMPERATURE DETECTOR AND CONTROLLING HEAT - A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET. | 02-05-2015 |
20150074627 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor. | 03-12-2015 |
20150108610 | NEARLY BUFFER ZONE FREE LAYOUT METHODOLOGY - In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities. | 04-23-2015 |
20150110158 | 3D THERMAL DETECTION CIRCUITS AND METHODS - A circuit includes sensing circuitry including at least one sensing element configured to output at least one temperature-dependent voltage. A compare circuit is configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage. A control circuit is configured to generate at least one control signal in response to the intermediate voltage. A switching circuit is configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal having a pulse width that is based on a temperature sensed by the sensing circuitry. | 04-23-2015 |
20150115717 | MOS-BASED VOLTAGE REFERENCE CIRCUIT - A voltage reference circuit is provided that includes a first circuit, a second circuit and a third circuit. The first circuit has a first MOS transistor pair and the second circuit has a second MOS transistor pair. The first circuit is configured to provide a first voltage component that changes at a first rate having a first slope as a temperature to which the voltage reference circuit is subjected changes. The second circuit is configured to provide a second voltage component that changes at a second rate having a second slope as the temperature changes. The third circuit is configured to use the first voltage component and the second voltage component to generate the reference voltage component that changes at a fifth rate having a fifth slope as the temperature changes. The fifth slope is substantially equal to zero to promote insensitivity of the reference voltage component to temperature changes. | 04-30-2015 |
20150177327 | In Situ on the Fly On-Chip Variation Measurement - A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation. | 06-25-2015 |
20150234964 | PATTERN DENSITY-DEPENDENT MISMATCH MODELING FLOW - In some embodiments, in a method, a layout of a circuit is received. A netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively, is generated using the layout. A simulation on the netlist is performed such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads. | 08-20-2015 |
20150268297 | CIRCUIT AND METHOD FOR MEASURING THE GAIN OF AN OPERATIONAL AMPLIFIER - A circuit for measuring the gain of an operational amplifier is provided. The circuit comprises a first operational amplifier, a first resistive device and a second resistive device. The first operational amplifier has an original gain and includes a first input terminal and a second input terminal. The first resistive device is coupled between the first input terminal and the second input terminal of the first operational amplifier. The second resistive device is coupled to the second input terminal of the first operational amplifier. The first resistive device and the second resistive device are configured to reduce a predetermined amount of gain from the original gain of the first operational amplifier. | 09-24-2015 |
20150356235 | GENERATING A SEMICONDUCTOR COMPONENT LAYOUT - A method includes generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also includes generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further includes manufacturing a semiconductor device having semiconductor components arranged based on one of the configurations of the second set of configurations. | 12-10-2015 |
20150362539 | OUTPUT RESISTANCE TESTING STRUCTURE AND METHOD OF USING THE SAME - A testing structure includes a first transistor having a first dopant type connected to a current source. The testing structure further includes a second transistor having a second dopant type, opposite to the first dopant type. The second transistor is connected to a device under test (DUT). The second transistor is connected in series with the first transistor in a cascode arrangement. The cascode arrangement is capable of measuring an output resistance of the DUT of greater than 1 mega-ohm (MΩ). | 12-17-2015 |
20150362540 | CIRCUIT AND METHOD FOR GAIN MEASUREMENT - A circuit for measuring a gain of an amplifier includes a first node coupled to an output of the amplifier, a second node, a first circuit coupled to an input and the output of the amplifier, and a second circuit coupled between the first circuit and the second node. The first circuit is configured to cause a first gain drop in a gain to be measured between the first node and the second node. The second circuit configured to cause a second gain drop in the gain to be measured between the first node and the second node. | 12-17-2015 |
20150362541 | CIRCUIT AND METHOD FOR BANDWIDTH MEASUREMENT - A circuit for measuring a bandwidth of an amplifier includes a switch-capacitor circuit and a controller. The switch-capacitor circuit is coupled to an output and an input of the amplifier. The switch-capacitor circuit is switchable between a sampling mode and an amplification mode. The controller is coupled to the switch-capacitor circuit and the output of the amplifier. The controller is configured to switch the switch-capacitor circuit between the sampling mode and the amplification mode, control the amplification mode to have various durations, and determine the bandwidth of the amplifier based on the various durations of the amplification mode and corresponding voltages at the output of the amplifier. | 12-17-2015 |
20150370946 | METHOD OF DENSITY-CONTROLLED FLOORPLAN DESIGN FOR INTEGRATED CIRCUITS AND INTEGRATED CIRCUITS - A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule. | 12-24-2015 |
20160035715 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM - A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other. | 02-04-2016 |
20160074828 | INTEGRATED CIRCUIT HAVING TEMPERATURE-SENSING DEVICE - An integrated circuit includes a plurality of sensing pixels. Each sensing pixel of the plurality of sensing pixels includes a sensing film portion, a potential-sensing device configured to generate a first signal responsive to an electrical characteristic of the sensing film portion, a temperature-sensing device configured to generate a second signal responsive to a temperature of the sensing film portion, and one or more heating elements configured to adjust the temperature of the sensing film portion. | 03-17-2016 |
Yu-Ren Peng, Hsinchu TW
Patent application number | Description | Published |
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20140070250 | LIGHT-EMITTING DEVICE - A light-emitting device of an embodiment of the present application comprises a substrate; a first semiconductor light-emitting structure formed on the substrate, wherein the first semiconductor light-emitting structure comprises a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type and a first active layer formed between the first semiconductor layer and the second semiconductor layer, wherein the first active layer is capable of emitting a first light having a first dominant wavelength; and a first thermal-sensitive layer formed on a path of the first light, wherein the first thermal-sensitive layer comprises a material characteristic which varies with a temperature change. | 03-13-2014 |
Yu-Yun Peng, Hsinchu TW
Patent application number | Description | Published |
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20130256903 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A interconnect structure includes a conductive layer formed in a dielectric layer. An adhesion layer is formed between the dielectric layer and a substrate. The adhesion layer has a carbon content ratio greater than a carbon content ratio of the dielectric layer. | 10-03-2013 |