Patent application number | Description | Published |
20110210443 | SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION AND METHOD OF FORMING SAME - An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated. | 09-01-2011 |
20110291287 | THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE - A device has a silicon substrate with a via extending from a first surface of the silicon substrate having a conductor portion. A first dielectric portion surrounds the conductor portion. A second dielectric portion is disposed between a first silicon portion and the silicon substrate. | 12-01-2011 |
20120032326 | AIR THROUGH-SILICON VIA STRUCTURE - A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate. | 02-09-2012 |
20120139083 | POWER DISTRIBUTION NETWORK - In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto. | 06-07-2012 |
20130181360 | INTEGRATED CIRCUIT CONNECTIVITY USING FLEXIBLE CIRCUITRY - An integrated circuit (IC) structure can include an internal element and a flexible circuitry directly coupled to the internal element. The flexible circuitry can be configured to exchange signals between the internal element and a node external to the IC structure. | 07-18-2013 |
20130277099 | CONDUCTOR STRUCTURE WITH INTEGRATED VIA ELEMENT - An electrical circuit structure can include a first trace formed using a first conductive layer and a second trace formed using a second conductive layer. The first trace can be vertically aligned with the second trace. The electrical circuit structure can include a via segment formed of conductive material in a third conductive layer between the first conductive layer and the second conductive layer. The via segment can contact the first trace and the second trace forming a first conductor structure configured to convey an electrical signal in a direction parallel to the first conductive layer. | 10-24-2013 |
20140262440 | MULTI-LAYER CORE ORGANIC PACKAGE SUBSTRATE - A multi-layer core organic package substrate includes: a multi-layer core comprising at least two organic core layers, wherein two of the at least two organic core layers are separated by a core metal layer; a first plurality of build-up layers formed on top of the multi-core layer; and a second plurality of build-up layers formed below the multi-core layer. | 09-18-2014 |
20150187715 | SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATON AND METHOD OF FORMING SAME - A semiconductor device includes a first under-bump metallization (UBM) layer disposed over a bond pad, a dielectric layer above an interconnect layer having a via exposing at least a portion of the first UBM layer. A second UBM layer is disposed above the first UBM layer and forms a UBM bucket over the via. The first UBM layer and UBM bucket are configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated. | 07-02-2015 |