Patent application number | Description | Published |
20080212282 | METHOD AND APPARATUS FOR COOLING AN EQUIPMENT ENCLOSURE THROUGH CLOSED-LOOP LIQUID-ASSISTED AIR COOLING IN COMBINATION WITH DIRECT LIQUID COOLING - A method and an apparatus for cooling, preferably within an enclosure, a diversity of heat-generating components, with at least some of the components having high-power densities and others having low-power densities. Heat generated by the essentially relatively few high-power-density components, such as microprocessor chips for example, is removed by direct liquid cooling, whereas heat generated by the more numerous low-power or low-watt-density components, such as memory chips for example, is removed by liquid-assisted air cooling in the form of a closed loop comprising a plurality of heating and cooling zones that alternate along the air path. | 09-04-2008 |
20080215790 | Memory systems for automated computing machinery - Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub. | 09-04-2008 |
20080235942 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure. | 10-02-2008 |
20080259671 | 3-DIMENSIONAL INTEGRATED CIRCUIT ARCHITECTURE, STRUCTURE AND METHOD FOR FABRICATION THEREOF - An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement. | 10-23-2008 |
20080285697 | SYSTEM FOR PROVIDING OPEN-LOOP QUADRATURE CLOCK GENERATION - A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes. | 11-20-2008 |
20080307645 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure. | 12-18-2008 |
20080311768 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure. | 12-18-2008 |
20080313408 | LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION - A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive. | 12-18-2008 |
20090006683 | STATIC POWER REDUCTION FOR MIDPOINT-TERMINATED BUSSES - A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well. | 01-01-2009 |
20090006808 | ULTRASCALABLE PETAFLOP PARALLEL SUPERCOMPUTER - A novel massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. Novel use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node. | 01-01-2009 |
20090006873 | POWER THROTTLING OF COLLECTIONS OF COMPUTING ELEMENTS - An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer. | 01-01-2009 |
20090006899 | ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT - A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data. | 01-01-2009 |
20090007427 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 01-08-2009 |
20090013528 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cros s-section and is constituted of a dielectric elastomeric material. At least one sidewall of the interposer is slitted to facilitate the venting of gases and pressure therethrough. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 01-15-2009 |
20090045882 | SYSTEM FOR GENERATING A MULTIPLE PHASE CLOCK - A system for generating a multiple phase clock. The system includes a ring oscillator structure for generating multiple phases. The structure includes two or more unit oscillators, each unit oscillator implemented by a ring oscillator having M stages. The structure also includes a horizontal loop coupling the two or more unit oscillators to generate multiple phases. The number of phases generated is equal to the product of the number of unit oscillators and M. | 02-19-2009 |
20090049688 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 02-26-2009 |
20090070999 | METHOD OF PRODUCING A LAND GRID ARRAY (LGA) INTERPOSER STRUCTURE PROVIDING FOR ELECTRICAL CONTACTS ON OPPOSITE SIDES OF A CARRIER PLANE - A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 03-19-2009 |
20090081891 | METHOD OF PRODUCING LAND GRID ARRAY (LGA) INTERPOSER GROUPS OF DIFFERENT HEIGHTS UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and interposer groupings of different height being mounted on a first surface of said carrier plane. Each interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of each hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 03-26-2009 |
20090100664 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. A plurality of slots are formed in the sidewall of said interposer for the venting of gases and pressure therethrough. | 04-23-2009 |
20090119916 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 05-14-2009 |
20090187794 | SYSTEM AND METHOD FOR PROVIDING A MEMORY DEVICE HAVING A SHARED ERROR FEEDBACK PIN - A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line. | 07-23-2009 |
20090201064 | Phase Interpolator System and Associated Methods - A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section. | 08-13-2009 |
20090259713 | NOVEL MASSIVELY PARALLEL SUPERCOMPUTER - A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources. | 10-15-2009 |
20090277616 | METHOD AND APPARATUS OF WATER COOLING SEVERAL PARALLEL CIRCUIT CARDS EACH CONTAINING SEVERAL CHIP PACKAGES - A cooling or heat transfer apparatus and method is disclosed for cooling an electronic device. The apparatus includes a heat producing electronic device which may include an electronic circuit card with many heat sources. A heat transfer device is connected to the heat producing electronic device which is thermally communicating with the heat producing device for transferring heat from the heat producing device to the heat transfer device. A heat conduit is connected to the heat transfer device and thermally communicating with the heat transfer device for transferring heat to the heat conduit from the heat transfer device. A cooling housing is connected to the heat conduit and the cooling housing thermally communicating with the heat conduit for transferring heat to the cooling housing from the heat conduit. The apparatus enables the replacement of circuit cards in the field because it eliminates the need to apply thermal-interface materials. | 11-12-2009 |
20090303681 | COINED-SHEET-METAL HEATSINKS FOR CLOSELY PACKAGED HEAT-PRODUCING DEVICES SUCH AS DUAL IN-LINE MEMORY MODULES (DIMMs) - A heatsink structure and method for the cooling of closely spaced packaged heat-producing devices, such as dual-in-line memory modules (DIMMs). A folded sheet metal heatsink structure is provided which is constituted of a coined metallic material and which has a large plurality of waffle-shaped ridges extending therefrom constituting additional surface areas which are adapted to enable heat generated by hub chips to pass upwardly and then outwardly through waffle-like ridges and, thus, dissipated to the exterior, thereby imparting an improved degree of cooling to heat-producing components or devices. | 12-10-2009 |
20090313439 | MANAGING COHERENCE VIA PUT/GET WINDOWS - A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements. | 12-17-2009 |
20090320282 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 12-31-2009 |
20100000085 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 01-07-2010 |
20100005218 | ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM - A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames. | 01-07-2010 |
20100025010 | APPARATUS AND METHOD OF DIRECT WATER COOLING SEVERAL PARALLEL CIRCUIT CARDS EACH CONTAINING SEVERAL CHIP PACKAGES - A cooling apparatus, system and like method for an electronic device includes a plurality of heat producing electronic devices affixed to a wiring substrate. A plurality of heat transfer assemblies each include heat spreaders and thermally communicate with the heat producing electronic devices for transferring heat from the heat producing electronic devices to the heat transfer assemblies The plurality of heat producing electronic devices and respective heat transfer assemblies are positioned on the wiring substrate having the regions overlapping. A heat conduit thermally communicates with the heat transfer assemblies. The heat conduit circulates thermally conductive fluid therethrough in a closed loop for transferring heat to the fluid from the heat transfer assemblies via the heat spreader. A thermally conductive support structure supports the heat conduit and thermally communicates with the heat transfer assemblies via the heat spreader transferring heat to the fluid of the heat conduit from the support structure. | 02-04-2010 |
20100121994 | STACKED MEMORY ARRAY - A memory subsystem, array controller, method, and design structure are provided for a stacked memory array. The memory subsystem includes an array controller and at least one memory array. The array controller includes a primary and secondary buffer interface to communicate with a memory controller via a cascade interconnected bus. The array controller also includes an array access controller to process memory access commands received via one of the primary and secondary buffer interfaces. The at least one memory array includes a memory cell array die separately packaged with respect to the array controller and coupled to the array controller in a stacked configuration via memory core data lines using through silicon vias (TSVs). | 05-13-2010 |
20100138684 | MEMORY SYSTEM WITH DYNAMIC SUPPLY VOLTAGE SCALING - A memory controller, memory device, and method for dynamic supply voltage scaling in a memory system are provided. The method includes receiving a request for a supply voltage change at the memory controller in the memory system, the supply voltage powering the memory device. The method further includes waiting for any current access of the memory device to complete, and disabling a clock between the memory controller and the memory device. The method also includes changing the supply voltage responsive to the request, and enabling the clock. | 06-03-2010 |
20100279521 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 11-04-2010 |
20100293436 | System for Error Control Coding for Memories of Different Types and Associated Methods - A system to improve error control coding may include memory chips of at least two different kinds. The system may also include error control encoder circuitry to substantially encode data for storage in any memory rank. The system may further include error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder. | 11-18-2010 |
20110055671 | ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY - An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device. | 03-03-2011 |
20110072219 | MANAGING COHERENCE VIA PUT/GET WINDOWS - A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements. | 03-24-2011 |
20110119521 | REPRODUCIBILITY IN A MULTIPROCESSOR SYSTEM - Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state. | 05-19-2011 |
20110171466 | PRECAST THERMAL INTERFACE ADHESIVE FOR EASY AND REPEATED, SEPARATION AND REMATING - Precast curable thermal interface adhesives facilitating the easy and repeatable separation and remaining of electronic components at thermal interfaces thereof, and a method for implementing the foregoing repeatable separation and remating at the thermal interfaces of components through the use of such adhesives. | 07-14-2011 |
20110172984 | EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION - A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off. | 07-14-2011 |
20110173413 | EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK - Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure. | 07-14-2011 |
20110173432 | RELIABILITY AND PERFORMANCE OF A SYSTEM-ON-A-CHIP BY PREDICTIVE WEAR-OUT BASED ACTIVATION OF FUNCTIONAL COMPONENTS - A processor-implemented method for determining aging of a processing unit in a processor the method comprising: calculating an effective aging profile for the processing unit wherein the effective aging profile quantifies the effects of aging on the processing unit; combining the effective aging profile with process variation data, actual workload data and operating conditions data for the processing unit; and determining aging through an aging sensor of the processing unit using the effective aging profile, the process variation data, the actual workload data, architectural characteristics and redundancy data, and the operating conditions data for the processing unit. | 07-14-2011 |
20110173488 | NON-VOLATILE MEMORY FOR CHECKPOINT STORAGE - A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card. | 07-14-2011 |
20110219208 | MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER - A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency. | 09-08-2011 |
20110219280 | COLLECTIVE NETWORK FOR COMPUTER STRUCTURES - A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm. | 09-08-2011 |
20120151171 | PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY - A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator. | 06-14-2012 |
20120151172 | PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY - A method for providing frame start indication that includes receiving a data transfer via a channel in a memory system. The receiving is in response to a request, and at an indeterminate time relative to the request. It is determined whether the data transfer includes a frame start indicator. The data transfer and “n” subsequent data transfers are captured in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers make up a data frame, where “n” is greater than zero. | 06-14-2012 |
20120266008 | SYSTEM-WIDE POWER MANAGEMENT CONTROL VIA CLOCK DISTRIBUTION NETWORK - An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command. | 10-18-2012 |
20120276375 | PRECAST THERMAL INTERFACE ADHESIVE FOR EASY AND REPEATED, SEPARATION AND REMATING - Precast curable thermal interface adhesives facilitating the easy and repeatable separation and remaining of electronic components at thermal interfaces thereof, and a method for implementing the foregoing repeatable separation and remating at the thermal interfaces of components through the use of such adhesives. | 11-01-2012 |
20120300563 | ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY - An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device. | 11-29-2012 |
20120300570 | ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY - An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device. | 11-29-2012 |
20120311299 | NOVEL MASSIVELY PARALLEL SUPERCOMPUTER - A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. | 12-06-2012 |
20140122980 | COLLECTIVE NETWORK FOR COMPUTER STRUCTURES - A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm. | 05-01-2014 |